mixed_signals
Junior Member level 1
Hello All,
I am designing a reference voltage buffer for an asynchronous 10-bit SAR ADC with 50MHz sampling rate.
The settling behavior of the reference buffer (especially at MSB cap switching) affects the linearity (ENOB). I am thinking of two ways:
1- Increase the bandwidth of the buffer by minimizing the load capacitance and maximizing the power to get the highest BW possible to achieve the minimum settling time (even the voltage undershoot is large during the MSB switching).
2- Increase the output capacitance (by adding large on-chip Decaps) that will minimize the voltage undershoot during the switching however it will reduce the achievable BW by moving the non-dominant pole to lower frequency.
So in summary which is better for the settling time for my target resolution: Higher BW but with higher voltage undershoot or Lower BW but with lower voltage undershoot??
Thank you in advance!
I am designing a reference voltage buffer for an asynchronous 10-bit SAR ADC with 50MHz sampling rate.
The settling behavior of the reference buffer (especially at MSB cap switching) affects the linearity (ENOB). I am thinking of two ways:
1- Increase the bandwidth of the buffer by minimizing the load capacitance and maximizing the power to get the highest BW possible to achieve the minimum settling time (even the voltage undershoot is large during the MSB switching).
2- Increase the output capacitance (by adding large on-chip Decaps) that will minimize the voltage undershoot during the switching however it will reduce the achievable BW by moving the non-dominant pole to lower frequency.
So in summary which is better for the settling time for my target resolution: Higher BW but with higher voltage undershoot or Lower BW but with lower voltage undershoot??
Thank you in advance!