the8thhabit
Member level 1
I am currently designing and layout a 10-bit SAR ADC circuit.
In the figure above, the brown and purple lines represent the top plate nodes that switch during operation (i.e., Vinp and Vinn).
One issue I'm facing is that when I compare the presimulation (presim) and postsimulation (posim) waveforms, not only is the sampling not performed correctly, but also the voltage difference during CDAC switching is smaller than expected. In the presim results, the switching occurs with a 0.5 Vref difference (0.88 V and 0.44 V), but in the posim results, the switching is about 0.1 V less than expected. I believe this is due to the parasitic capacitance introduced in the layout, which is affecting the CDAC switching. Could you suggest layout techniques to reduce parasitic capacitance?
