Sampling Duty Cycle & Switch linearity

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shico90

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Hello, Is there a conditiong for the duty cycle of the sampling frequency. I know that the sampling frequency should be twice or more the signal frequency but what about the duty cycle. Does it have to be 50%? when I make it 50% I have good linearity with the sampling NMOS switch but when I make it 15% I have really bad linearity with high distortion. Can anyone help please?
 

Usually its 50% Duty Cycle and most ADC's use a leading edge to clock and you want to maintain that to keep slew from effecting you.
However your sample rate should be about 10X in maximum incoming frequency you wish to sample in order to get a good result. Since the input signal is usually not synchronized with the sample rate, you can easily get a distorted capture that's not representative to the actual input signal.
I did a lot of work with Analog to digital conversion of voice to transmit digitally over the air and then reconvert it back to voice.
To do it properly and maintain signal coherency we used a sample rate of about 200khz. Which is audio max 20khz x 10.
 

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