Sample rate calculation

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Hi everyone,

I have a basic question I am hoping if anyone can help me with.
How to calculate the sample rate .i.e how many sample per second if I have 100 MHZ clock, 12-bit resolution and the conversion time is 40 Usec. This is not a HW, I'm just using ADC and it gives me this but I don't know what is the sample rate I have.

I did this calculation but not sure it is correct

12/(40*10^-6) = 300 KBPS

Thanks
 

You're getting your brain tied in a knot. The 100MHz clock is irrelevant, as is your 12 bit sample size. Your sample rate (maximum) is 1/40uSEC=25K-samp/sec. This assumes that you are sampling continuously.
 
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    icd

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Thanks Barry. I have one more question.

I got the 40 usec conversion time from this equation (2^N)/Fclk, where N is the number of bits needed. So in my case (2^12)/100MHZ =40 usec. You mentioned to that the sample rate is the reciprocal of the conversion time. if this is correct, does that mean to increase the sample rate I need to either decrease the number of bits or increase the Fclk ?!!! Also are they (No of bits & Fclk) limited to a specific number ?
 

May be you are talking about a Sigma Delta ADC ?
In that case you will have an input sampling rate and an output sampling rate (data rate). Then the output rate will depend on the filter/decimator that you implement to get the number of bits of resolution that you want.
I think that the output rate will be fsamp/N. But let me check that.
 
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    icd

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Regardless what type of ADC you are using, sample rate is, by definition, simply (I hope this doesn't sound too stupidly obvious) the rate at which samples come out of the device-it doesn't matter how they got there.

Now, as Albert says, the sample rate DOES depend on the clock rate for a Sigma delta (and other ADCs as well). The sample size is usually not controllable, it's specific to the device. In other words, you can have a 12-bit ADC and run it with different clock inputs and you'll get proportionally different sample rates.
 
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    icd

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Here is the reason I asked my question. I tried to write a VHDL code for the structure of the ADC I am attaching.


In fig "b" the author claimed that we can either increase the speed or the resolution by multi-sampling as u see in the figure "b". But when I wrote the code I found out I can increase the speed just by increasing the rate of the main clock and also u see the register and the counter both are working under the main clock. So there is something I don't understand here. Hopefully u guys can help me with.

The link of the paper. It's the first two pages:
https://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6154442
 

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