sample&hold + flash adc !!help!!

[ljy4468]

hi everybody
i have a big problem with my circuit.
please give me answer.

I've designed 2bit flash adc.
and that's operating well.

and i have made sample & hold circuit with ideal opamp
it also working well too.

but attached s&h to adc.
it doesn't work well.

for example,
holded voltage is 1.73V
So, flash ad comparator output must be 011 (thermometer code)
( my reference voltage is 1.4V 1.65V 1.9V) (1.15~ 2.15 range)

but thermometer output is 001
reference oscillate is less than 1%.

why is that happen?

I applied input voltage 1.73V to 2bit flash adc without s&h
output is 011 (works well)
why it doens't work with s&H?????

please give me answer~~~~~
hellp me

have a good day
thanks

 

[ocarnu]

When you latch the comparators, does the output of the SH fluctuate? I am thinking you might have some kind of charge transfer. even though, with ideal opamp that shoudn't happen. So, chech the output of the SH in HOLD phase: is it the same connected to the ADC as when it is alone?

 

[sunking]

check the s&h and adc clock timing.

 

[winsonpku]

can you post your S&H made in ideal opamp
and the clocks and connetctinos between the flash adc
so maybe that can describes the problems more clearly.

hi everybody
i have a big problem with my circuit.
please give me answer.

I've designed 2bit flash adc.
and that's operating well.

and i have made sample & hold circuit with ideal opamp
it also working well too.

but attached s&h to adc.
it doesn't work well.

for example,
holded voltage is 1.73V
So, flash ad comparator output must be 011 (thermometer code)
( my reference voltage is 1.4V 1.65V 1.9V) (1.15~ 2.15 range)

but thermometer output is 001
reference oscillate is less than 1%.

why is that happen?

I applied input voltage 1.73V to 2bit flash adc without s&h
output is 011 (works well)
why it doens't work with s&H?????

please give me answer~~~~~
hellp me

have a good day
thanks

 

[noiseless]

sunking maybe right. check the timing.

another thing is settling time is a problem?

 

[ezt]

Hi.
1.73 - 1.65 = 80 mV
80mV is not very low but this really depends on the comparator offset. As you said, comparators work well, but if S/H stage introduces just a little bit error to the held voltage, this difference may become less and your comparator may not recognize this difference due to its offset. But you said the S/H opamp is ideal, but check its output again and see if its ess (steady state error) is zero. Or you can give a larger voltage like 1.8 V as the input and check if output is 011.
Besides, your ref voltages show that your flash adc is working in 3.3 V. and VFS = 1 V (VFS = Vref+ - Vref-). but you have chosen VFS/4, VFS/2 and 3*VFS/4 as comparator ref voltages. As you know this will lead to a quantization noise with a non-zero mean value. (you can change ref voltages to 1.275, 1.525 and 1.775 V).

Regards,
EZT

 

[ocarnu]

The input voltage can have it's own DC component, is not necessary to be around 0.

 

[ljy4468]

Thank you every body!!
thankyou

i solved this problem
the problem is clock timing
my comparator clock get data just after hold data.
e.g. hold....after 1ns,,, comparator in adc begin to compare. -> not working

but comparator compare after 1.3ns, working well
it's the clock timing problem.
but i don't know why compare 1.3ns after hold phase..

anyway thank you
~

 

[ocarnu]

It seems that the comparator needs some time to get a correct voltage at the internal nodes. Otherwise it does not settle and the latched value is wrong. This why you have a minimum (1.3ns) necessary for settling.

 

[gxzhou]

nod.
Additionally, the time is different under different corner,temperature,power supply

It seems that the comparator needs some time to get a correct voltage at the internal nodes. Otherwise it does not settle and the latched value is wrong. This why you have a minimum (1.3ns) necessary for settling.