Sample Delay in FIR Filters

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Sandrokottus

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Hi, I am new to verilog and am trying to simulate and synthesize an FIR filter. Now the filter equation is- y=ax+bx(n-1)+cx(n-2)+.....
My question is basically how to produce x(n-1), x(n-2) and so on from x. In some literature, pipeline delays have been mentioned. I just want a simple model that can reproduce the x(n-1), etc.. Is producing x(n-1), x(n-2),etc. same as 1 clock cycle delay, 2 clock cycle delay, etc? Kindly help
 

use a shift register. THen you have access to X(n-m), where m is the length of the shift register.
 
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