same circuit in different technologies

Hey guys,

I have a question concerning different cmos technologies. First of all im very unexperienced. If i want to build a circuit in cadence in 2 different technologies lets say 40nm cmos and 130nm cmos using the same device sized for my transistors what are the main reasons that both circuits wont "behave" the same way?
For example if i use 40nm technology and chose channel lenght of 130nm for all my devices and do it the same way for 130 nm technology it wont work that way in the latter case.
Is there maybe a rule of thumb how to "scale" switching between different technologies?

Hi mirror_pole

Different technologies implies in different process parameters. It is not limited for different tech nodes, but also for the same node from different foundries (let's say, TSMC180nm and GF180nm, for example).

The main reason dwells on process parameters as the concentration of impurities during the doping; impurities in the oxide interface; types of passive components available; type of field oxide (for example, hi-K). Besides that, the manner how those parameters varies statistically also differs one tech for the other.

Kind regards,
Vitor

hey thanks for your answer, i kinda get an idea but i guess this requires pretty good knowledge of the physics behind it. I tried to copy the device dimensions of a circuit build in 40nm technology with 130nm technology and noticed that it simply didnt work. Tried to "scale" it from there, also using the same scale factor between the lenght they used and their min lenght and it worked somehow. Still would like to know if there is some rule of thumb but i guess due to complexity it would be hard to tell.

I guess threshold voltages also depend on technology? Does this mean that for example for low voltage/supply design newer technologies are better, allowing to stack more devices?

mirror_pole said:

Still would like to know if there is some rule of thumb but i guess due to complexity it would be hard to tell.

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In fact, there's no rule of thumb for it. You need basically know well the functioning of the working you are porting from one technology to another, then you will be able to judge what parameters have more impact in your specifications. Just to give you a perspective, there are people whose job basically comes down to port circuits from a technology to another.

mirror_pole said:

I guess threshold voltages also depend on technology?

Click to expand...

Yes, you're absolutely right, the threshold voltage has a direct relation with doping and gate's oxide impurities - I can suggest you the chapter 6 of Streetman's book: Solid State Electronic Devices.

You can also take a look at the first chapter of most of the microelectronics books to have a basic introduction to some devices physics, it is pretty fun and also pretty usefull to start. I can suggest you Gray's book (Analysis and Design of Analog Integrated Circuits) first chapter. I guess it is a good start point.

Regards,
Vitor

mirror_pole said:

I guess threshold voltages also depend on technology? Does this mean that for example for low voltage/supply design newer technologies are better, allowing to stack more devices?

Click to expand...

Newer technologies are better in some respect and worse in other. You can generally get more gm for the same current density and they are faster. But they have lower gds, so not so much intrinsic gain for the devices. They work with lower supply voltages, which means you can't stack more devices. For example if you have 1um technology that works at 5V you can cascode maybe 3 devices, or 4. If you have 28nm with 1V supply you can't stack more than one cascode.
Newer technologies match better for the same device area. Usually they have worse flicker noise.

sutapanaki said:

Newer technologies are better in some respect and worse in other. You can generally get more gm for the same current density and they are faster. But they have lower gds, so not so much intrinsic gain for the devices. They work with lower supply voltages, which means you can't stack more devices. For example if you have 1um technology that works at 5V you can cascode maybe 3 devices, or 4. If you have 28nm with 1V supply you can't stack more than one cascode.
Newer technologies match better for the same device area. Usually they have worse flicker noise.

Click to expand...

Hey i guess u mean rds(and therefore gds=1/rds) and not the capacitance gds am i right? So because of the more pronounced channel lenght modulation rds goes down which means less self gain?

could you explain the stacking device part again i didnt get that. So downscaling technology means also that the allowable supply decreases?

Yes, gds, rds, ro - same thing, of course gds=1/r0. It is not only the channel length modulation that plays a role in lowering ro. In finer technologies there are short-channel effects like DIBL that also bring about lower output resistance. For example, the FinFET transistors solve the problems with DIBL and as a consequence they have higher ro and higher intrinsic gain although L is 16nm and below.

Newer technologies have for example thinner gate oxide which can't sustain higher electric fields, hence lower supply voltages. Digital circuits have VGS=Vdd or 0, all the Vdd is across the gate oxide. Shorter channel lengths and high supplies along them also cause hot carrier problems.

Suppose you build a current mirror and you want to cascode, say 2 nmos transistors on top of the mirroring device and say your supply is 1V and you want to have min voltage across the mirror of 0.5V. Let's say Vth=0.4V. Suppose you want to keep 0.15V as Vov for each of the 3 devices in the mirror. So, 3x0.15=0.45 and you are almost at your limit of 0.5V. Of course you have to leave something in excess of Vov=0.15 for the Vds of the transistors to have more reliable operation and margin. And thus very quickly you get to or above your 0.5V limit. Also, 0.5 is quite generous, you don't usually have that much.
Then, you will have to bias the gates of the cascodes. If the bottom mirroring device works with Vds=Vov=0.15 and Vth=0.4, then for the first cascoding transistor Vg=0.15+0.4=0.55. Again, for reliable operation somewhat more than that. Going further up, at the source of the top casode transistor you will have something like 2x0.15=0.3V and its gate has to be at 0.3+0.4=0.7 which is getting closer to your supply limit of 1V. If you leave margin in your Vgs, then you hit the supply.
Add to all this also operation in slow corner, high temperature.
It means that usually you get by with one cascode only.

Semiconductor Manufacturing is so weird so that exactly same process manufactured in 2 different factories are not same at all..
Different processes are so far..Converting from one to another is almost impossible even for loosest specifications