S22 not matching simulation

[arwen16]

Hello,

I had designed an LNA using an HBT from Infineon on ADS and had it fabricated and tested. The S11 measured was a good match with thr simulation results. However, the S22 measured looked like a flipped version of the S22 simulated. I don't know how to debug this issue.

 

[volker@muehlhaus]

If you (with all information about your design and results) don't know how to debug this, how can we (with no information) help you?

 

[arwen16]

If you (with all information about your design and results) don't know how to debug this, how can we (with no information) help you?

Hello, I just wanted to know if anyone has ever experienced this and maybe wanted to know what possible reasons could there be for S22 not matching the simulated results. If you have any questions about my circuit design, please let me know.

 

[arwen16]

Hello,

I had designed an LNA using an HBT from Infineon on ADS and had it fabricated and tested. The S11 measured was a good match with thr simulation results. However, the S22 measured looked like a flipped version of the S22 simulated. I don't know how to debug this issue.

The output side consists of an series SMD resistor connected in parallel to a series RC for stability and matching network was designed using microstrip line.

 

[BigBoss]

"Flipped version" ?? Is |S22|>1 ?

 

[arwen16]

"Flipped version" ?? Is |S22|>1 ?

No no..S22 is below -10dB. By flipped I mean, the dip in response that was expected at higher frequency (as seen in my simulation) now appears in the lower frequency( as seen is my measured results). The dip is actually a prominent dip, hence I can't even ignore it.

 

[FvM]

I would at least expect
- circuit schematic
- simulated versus measured S22

 

[arwen16]

Hello,

1. As the design is a part of research work, I will be unable to share the same.
2. I have attached the S22 response of the circuit.

 

[BigBoss]

The difference is huge and not acceptable. There must be an either a design error or component tolerance/manufacturing error. It might be a crack or wrong labeled etc.
I'd change the components that seem non-adequate.

 

[arwen16]

The difference is huge and not acceptable. There must be an either a design error or component tolerance/manufacturing error. It might be a crack or wrong labeled etc.
I'd change the components that seem non-adequate.

I wanted to understand what you mean by design error as I got the results in EM simulation. Am I doing the simulation wrong?

 

[FvM]

I wanted to understand what you mean by design error as I got the results in EM simulation. Am I doing the simulation wrong?

You are claiming to show simulation versus measurement. Now you tell, the "measurement" is actually a simulation?

 

[arwen16]

No, the plot I shared is the measurement result vs EM simulation result only. I assumed when the user said "design error" he meant while I was designing the circuit at the simulation stage. Hence, I needed the clarification.

 

[Yigit Yalcinkaya]

No, the plot I shared is the measurement result vs EM simulation result only. I assumed when the user said "design error" he meant while I was designing the circuit at the simulation stage. Hence, I needed the clarification.

Arwen, When you chose RC and the lumped component did you pay attention to the lumped component's tolerance? Like rated voltage, X7R, X5R, and SRF specifications. The actual PCB is affected by solder, connector, etc.

 

[FvM]

No, the plot I shared is the measurement result vs EM simulation result only.

Thanks for clarification. Design error could mean that the features you are simulating, e.g. TL for impedance matching are not implemented appropriately in PCB. Or that the PCB has parasitic elements not reflected in the simulation, as proposed in above post. I think, it's impossible to advance in the discussion without knowing at least the kind of used matching elements and also the intended operation frequency range.

 

[arwen16]

Arwen, When you chose RC and the lumped component did you pay attention to the lumped component's tolerance? Like rated voltage, X7R, X5R, and SRF specifications. The actual PCB is affected by solder, connector, etc.

Yes, I did.

Thanks for clarification. Design error could mean that the features you are simulating, e.g. TL for impedance matching are not implemented appropriately in PCB. Or that the PCB has parasitic elements not reflected in the simulation, as proposed in above post. I think, it's impossible to advance in the discussion without knowing at least the kind of used matching elements and also the intended operation frequency range.

The LNA has been designed to operate in the 2-3.5 GHz range. The matching was done using microstrip lines only. Is it possible that the transistor model I used is inaccurate?

Thanks for clarification. Design error could mean that the features you are simulating, e.g. TL for impedance matching are not implemented appropriately in PCB. Or that the PCB has parasitic elements not reflected in the simulation, as proposed in above post. I think, it's impossible to advance in the discussion without knowing at least the kind of used matching elements and also the intended operation frequency range.

 

[BigBoss]

Yes, I did.

The LNA has been designed to operate in the 2-3.5 GHz range. The matching was done using microstrip lines only. Is it possible that the transistor model I used is inaccurate?

Yes, it's possible. Which transistor have you used ? What about the substrate ? Could you find the substrate that you intend to use ? Are their specifications correct ? ( substrate height, di-electric coefficient etc.) Is there any problem while manufacturing ?
How about the VNA calibration ? Is it well done ?

Very extreme microstrip line dimensions are generally error sources such as very thin lines, very short/ very long stubs. They are seem to be correct in EM simulations but they might be very troublesome in practical measurements because of manufacturing process.

 

[volker@muehlhaus]

I got the results in EM simulation. Am I doing the simulation wrong?

From my 20+ years work in EM simulation support: If your measurement does not agree with simulation, you have not built what you have simulated.

You are not able or willing to discuss what you did, so how can we tell you where you might have made a mistake? I have seen all sorts of user mistakes, most often related to ports and coarse meshing.

 

[arwen16]

I have used the BFP740FESD HBT from Infineon. I used an FR-4 substrate of 1.6mm thickness.

 

[volker@muehlhaus]

FR-4 substrate of 1.6mm thickness.

What permittivity did you use for simulation? FR4 is known for very large tolerances of permittivity. Also, the fibre pattern can have a large influence.

In general, this is a bad choice for transmission line circuits in your frequency band of interest.

 

[arwen16]

Yes, it's possible. Which transistor have you used ? What about the substrate ? Could you find the substrate that you intend to use ? Are their specifications correct ? ( substrate height, di-electric coefficient etc.) Is there any problem while manufacturing ?
How about the VNA calibration ? Is it well done ?

Very extreme microstrip line dimensions are generally error sources such as very thin lines, very short/ very long stubs. They are seem to be correct in EM simulations but they might be very troublesome in practical measurements because of manufacturing process.

From my 20+ years work in EM simulation support: If your measurement does not agree with simulation, you have not built what you have simulated.

You are not able or willing to discuss what you did, so how can we tell you where you might have made a mistake? I have seen all sorts of user mistakes, most often related to ports and coarse meshing.

What permittivity did you use for simulation? FR4 is known for very large tolerances of permittivity.
In general, this is a bad choice for transmission line circuits in your frequency band of interest.

I used 4.3 as the permittivity of FR-4. I understand that the substrate is not ideal. However, since the LNA design is a part of research work, we wanted to first test the proof of concept of a cheap substrate and then move on to better options like Rogers, Taconic, etc.

--- Updated Sep 4, 2023 ---

From my 20+ years work in EM simulation support: If your measurement does not agree with simulation, you have not built what you have simulated.

You are not able or willing to discuss what you did, so how can we tell you where you might have made a mistake? I have seen all sorts of user mistakes, most often related to ports and coarse meshing.

I have covered the part relevant to my research. In the first picture, I have used this to generate my EM results and then done the EM co-simulation later. I did not incorporate the vias at this point. I simulated from 0 to 12 GHz and used 60 cells/wavelength in the EM setup. The second picture is what I gave for fabrication with the vias. The bias network worked just fine. I got the exact collector current. The S11 measured also agreed well with the measurement results.