S/H circuit - design sample and hold circuit for ADC help

[Monady]

h circuit

i have to design sample and hold circuit for ADC with this spec:1000MSPS and 8bit resolution.input of this circuit(S/H) is single ended(Vi) and output is single ended too.
most of S/H that i saw in papers are fully differential thus are useless for me.
any suggestion will be so useful.

 

[Guest]

Re: S/H circuit

you can simply use a t-gate as switch sampler for a sampling cap.

however, you have to choose correct sizing for its transistors (to minimize clock feed-through, charge injection, and any harmful effects); a true clock must be defined, preferably a non-overlapping one with real rise/fall times (I suggest you using of real clock generation). I also suggest you testing your simple S/H circuit dynamic performance separately (THD, etc.).

Good luck

 

[Monady]

S/H circuit

Thanks for your reply.
dear buddy, my circuit works in 1GHz, in this situation assume that 10PF cap used for sampling capacitor(it seems,this value is reasonable), thus in 0.5ns, cap must charge and track input voltage.it seems that in this situation, time constant of this circuit must be so small(for example, MOS On-resistance must be lower than 10ohm) and i think that reaching to this value is not accessible.

 

[platforma]

Re: S/H circuit - design sample and hold circuit for ADC hel

did you find solution for this problem?
What was your technology?

 

[Monady]

I designed the T/H in a 0.18um CMOS technology. For high speed applications, open loop T/H circuits are more suitable compared to the closed loop S/Hs . I used of a T/H compromises a NMOS switch and a samling capacitor in my ADC. BTW, using of fully differential architectures will be so useful specially from the kickback noise, clock feedthrough, ... standpoints.

 

[platforma]

in my topology Im using double sample and hold. ıts reason is using sample time with second S/H circuit. so with 500mhz s/h I will have 1GS/s signal. but in my topology ı have problems with opamp. What about your topology?

 

[Monady]

As i previously said, i did not use of S/H circuit in my ADC. Thus i have no any idea about your problem. but, take a look at this paper:
Norouzpour-Shirazi, A. Mirhaj, S.A. Ashtiani, S.J. Shoaei, O., "A Novel Low Power 1 GS/s S&H Architecture With Improved Analog Bandwidth,"
This paper appears in: Circuits and Systems II: Express Briefs, IEEE Transactions on
Publication Date: Oct. 2008
Volume: 55 Issue: 10
On page(s): 971 - 975

 

[platforma]

What is the main difference with s/h and t/h. thanks for your advice , I will look that paper.