RX FIFO size and alignment

[Ben_Beckman]

The RX FIFO in I2C Master is byte aligned? And what is the threshold value of it to assert the RX FULL interrupt according to the spec?

 

[KlausST]

Hi,

In my eyes the question makes not much sense.
1) because it surely depends on exact microcontroller type
2) meaningful values depend on application and thus on setup
3) but most of all: an I2C in master mode only receives data when it reqests data. The master starts and ends the communication by applying I2C_START and I2C_STOP. So actually the master knows from the beginning how much bytes to request and receive.

Usually
* I2C is not used for data streams, thus the bytes per communication is limited. (In opposite to UART for example)
* I2C slaves don't send data without request (in opposite to UART)

Klaus

I recommend to read about basic I2C operation and read microcontroller datasheet.