Runt clock pulse on a flop with static input

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prassingh

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Hi,

Will there be a glitch on output of a D flipflop when a runt pulse is applied to clk pin. The input data is assumed to be static.
 

Yes, Depends on the schematic you are designing.

But you can avoid the glitch by adjusting the pMOS and nMOS width.
 

I'm not designing any schematic.
I wanted to know this because I wanted to switch between asynchronous clocks to the flops . It is guaranteed that input will be stable at time of switching.
So if there will be glitch then certainly I need to gate clocks before switching and if not then there is no problem.
So could you please tell if there will be a glitch {possibly with some explanation} assuming master-slave flip-flop configuration ?
 

Yes, The glitch will be formed since the asynchronous clocks may reform with different delay.

Can you post your schematic here? .

Since you are not doing schematic, what is the purpose of this?. Because to understand in depth , it will be good if your working on schematic.
 

I'm working on some scan-debug flops where I need to switch between test clock and functional clocks. Input of such flops will be constant at time of switching . So if there will be a glitch even though data is constant there will be corruption of data in the chain. So that's why I wanted to confirm whether really there will be glitch or not . I thought that data is already latched so there should not be glitch at output of flop.
All flops are master-slave configuration (TSMC 28nm HPM process) .
 

Glitches will be present when there is transition from High to Low and Low to High and also due to elements used in Schematic. Due to mismatch of transistors.

Also care should be taken for asynchronous signals that , if they are to reform in the design there should not be any delay.

I am not very good at this all, but this is what i know,
 
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