Non AMP

Run VCS simulaton with SDF file

Thread starter abu9022
Start date Sep 22, 2014

Status: Not open for further replies.

Sep 22, 2014

#1

A

abu9022

Member level 3

Hi Friends

can you help me how to run VCS simulation with a SDF file

Sep 22, 2014

#2

J

jbeniston

Advanced Member level 1

vcs ... -sdf max:testbench.dut:your_file.sdf

Sep 23, 2014

#3

A

abu9022

Member level 3

jbeniston said:
vcs ... -sdf max:testbench.dut:your_file.sdf

we can run VCS simulation in modelsim(mentor graphics)?

Sep 23, 2014

#4

J

jbeniston

Advanced Member level 1

VCS is a simulator like ModelSim.

You can run an SDF simulation in ModelSim...

Status: Not open for further replies.

Similar threads

K
VCS Mixed Simulation VCS VHDL Verilog Mixed language simulation with UVM
- Started by Kashif Minhas
- Oct 8, 2024
- Replies: 6
ASIC Design Methodologies and Tools (Digital)
K
Unable to Dump VHDL Design Signals in VCD file Using VCS
- Started by Kashif Minhas
- Oct 22, 2024
- Replies: 2
ASIC Design Methodologies and Tools (Digital)
A
How to read .sdf or .db file to TetraMax for Slack-based trantision fault ATPG
- Started by Aisiki
- Nov 15, 2024
- Replies: 0
ASIC Design Methodologies and Tools (Digital)
C
vcs compilation option "-file" does not work.
- Started by coshy
- Jan 24, 2024
- Replies: 1
ASIC Design Methodologies and Tools (Digital)
A
VCS in EDA playground, not detecting module defined in another file
- Started by analog_malware
- Nov 30, 2023
- Replies: 2
ASIC Design Methodologies and Tools (Digital)