run time reconfiguration

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nikhilna007

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how can we perform run-time reconfiguration in fpga's?
 

This is the partial-reconfiguration feature. The exact build flow is based on the FPGA and vendor. The vendor should have the most up to date information on what features are supported and which ones are not.
 

permute said:
This is the partial-reconfiguration feature. The exact build flow is based on the FPGA and vendor. The vendor should have the most up to date information on what features are supported and which ones are not.
Click to expand...


which are the xilinx and altera fpga that support runtime recconfiguration.
 

Altera devices:

Stratix® V, Arria V and Cyclone V devices offer support for partial and dynamic reconfiguration

Xilinx devices:

Supports Virtex-4, Virtex-5, Virtex-6, Virtex-7, Kintex-7, Artix-7 FPGA families and the Zynq™-7000
 

shahulakthar said:
Altera devices:

Stratix® V, Arria V and Cyclone V devices offer support for partial and dynamic reconfiguration

Xilinx devices:

Supports Virtex-4, Virtex-5, Virtex-6, Virtex-7, Kintex-7, Artix-7 FPGA families and the Zynq™-7000
Click to expand...

thank you sir.

can you provide me some pdf to study about how to perform (steps for) some simple run time reconfiguration examples in these fpgs...
 

thank you

expecting more support from all....










you can find FPGA Kit and learning source at **broken link removed**[/QUOTE]
 

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