signal [B]dout_i [/B] : std_logic_vector(255 downto 0) := (OTHERS => '0');
signal [B]c0_app_wdf_data[/B] : std_logic_vector(C0_APP_DATA_WIDTH-1 downto 0);
begin
c0_app_wdf_data <= "000000"& not dout_i(255)& dout_i(254 downto 246)&
not dout_i(239) & dout_i(238 downto 230)&
not dout_i(223) & dout_i(222 downto 214)&
not dout_i(207) & dout_i(206 downto 198)&
not dout_i(191) & dout_i(190 downto 182)&
not dout_i(175) & dout_i(174 downto 166)&
not dout_i(159) & dout_i(158 downto 150)&
not dout_i(143) & dout_i(142 downto 128)&
"000000"& not dout_i(127)& dout_i(126 downto 118)&
not dout_i(111) & dout_i(110 downto 102)&
not dout_i(95) & dout_i(94 downto 86)&
not dout_i(79) & dout_i(78 downto 70)&
not dout_i(63) & dout_i(62 downto 54)&
not dout_i(47) & dout_i(46 downto 38)&
not dout_i(31) & dout_i(30 downto 22)&
not dout_i(15) & dout_i(14 downto 0);
wr_i_fifo_inst : wr_fifo_top
PORT MAP (wr_clk, rd_clk, rst, wr_en, rd_en, o_ichannel_data, [B]dout_i[/B], full_f1, empty_f1);