hi
yes it is declared within the interface
Here is the full interface
interface ram_if(input bit clock);
//Define all DUV ports as logic data type
logic read, write;
logic [7:0] wr_address, rd_address;
logic [15:0] data_in, data_out;
//Define Driver Clocking Block
clocking dr_cb@(posedge clock);
output data_in, rd_address, wr_address,read, write;
endclocking
//Define Receiver Clocking Block
clocking rcv_cb@(posedge clock);
input rd_address;
input data_out;
endclocking
// Driver Modport
modport DR_MP (clocking dr_cb);
// Receiver Modport
modport RC_MP (clocking rcv_cb);
endinterface