[SOLVED] Run Time error in questasim6.4c/Virtual interface resolution cannot find a matching

[Basu_Gouda]

Hi
I am using questasim 6.4c for my verification using system verilog and using coverage driven methodology.

I am facing an error as specified below
/lib/ram_env.sv(62): Virtual interface resolution cannot find a matching instance of interface 'ram_if.DR_MP'

I tried to sort out from some of the given solution in net but in vain please could somebody help me out

Thanks in advance

 

[paulki]

Can you please paste line no:62 of /lib/ram_env.sv to understand more about the issue. For top level, I believe some virtual interface declared and the hierarchical path for the same is not existing.

-paulki

 

[Basu_Gouda]

Can you please paste line no:62 of /lib/ram_env.sv to understand more about the issue. For top level, I believe some virtual interface declared and the hierarchical path for the same is not existing.

-paulki

virtual ram_if.DR_MP dr_if;// Virtual interface declared

line 62:repeat(5)
@(dr_if.dr_cb);

its just used to provide some delay before doin one or the other option

 

[paulki]

Check the interface "dr_if" for the signal "dr_cb" whether declared inside the interface.

 

[Basu_Gouda]

hi
yes it is declared within the interface

Here is the full interface
interface ram_if(input bit clock);

//Define all DUV ports as logic data type
logic read, write;
logic [7:0] wr_address, rd_address;
logic [15:0] data_in, data_out;

//Define Driver Clocking Block
clocking dr_cb@(posedge clock);
output data_in, rd_address, wr_address,read, write;
endclocking


//Define Receiver Clocking Block
clocking rcv_cb@(posedge clock);
input rd_address;
input data_out;
endclocking

// Driver Modport
modport DR_MP (clocking dr_cb);
// Receiver Modport
modport RC_MP (clocking rcv_cb);
endinterface