RTL optimization tips

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elec_student

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Hi,
I am facing some slack problem while synthesis of my RTL. I tried optimizing but not to much effect. Can anyone tell from where I can get some insight of various optimization techniques for improving delay in combinational blocks.

Thanks
elec
 

1. Look for if-elsif-elsif type statements : they are a recipe for un-necessary delays
2. Look for nested if(s) : again recipe of un-necessary delays:
In both the above cases you must ensure that these constructs are not intentional to implement a priority scheme, then replace them by case statements
3. Look for state registers: code them one-hot
4. Look for for-exit loops: again they introduce un-intentional priority schemes
5. Try to move logic before/after registers in the critical path.
6. And of course as suggested, pipelining can be introduced, if nothing works.
Hope it helps,
Kr,
Avi
http://www.vlsiip.com
 
I had problem with my 14bit adder as well.

Can you guys help? Thanks.
 

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