RTL design flow synthesis, verilog

can someone pls tell me the answers for the following questions pls
1. what is module instantiation in verilog?
i understand module is like a basic unit say for eg a flip-flop. i saw some verilog tutorials and it was told that modules are instantiated. does that mean that an existing module is placed into a higher module to create that higher module or wat exactly is the case... i'm totally confused can someone pls explain me with a simple example since i'm totally new to this.


2. why do we need to synthesize the RTL level to gate level. cant we directly implement in RTL level itself

3.what is post synthesis file created by synopsis.. i mean we synthesize our RTL design to get gate level netlist which is verified. it was put that post synthesis is required for verification. why do we have to verify it again

4. it was also put in the tutorial that this post synthesis file replaces the already loaded design file in the simulation. what does that mean

5. it comes in the order of system then RTL- gate level-circuit level- layout...... here system level is top and layout is the last end part for manufacturing the chip... we write verilog code in RTL level (we dont even go to the system level) then we synthesis and in the end fabricate the chip. my question is dont we have to build the system

3. For post-syn netlist, we need to verify it's function is the same with RTL code by using LEC/ Formality. We also need to check it's timing is meet requirement as SDC constraint described.