konstan
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Hi everyone,
I am using Faraday-90nm library. My lib_search path for tcl file is /Cadence/libraries/Faraday-90nm-Faraday90nm-SP/Design-Kits/2010/fs0a_a//2010Q4v2.1/GENERIC_CORE/FrontEnd/synopsys/synthesis and the target library is fs0a_a/generic_core_ff1p32vm40c.lib. The verilog file is a accu.v (accumulator). I am using the gui interface but when i run the tcl file my gates are unmapped. What is wrong? Am I using wrong target library?
Thank in advance,
Konstan
I am using Faraday-90nm library. My lib_search path for tcl file is /Cadence/libraries/Faraday-90nm-Faraday90nm-SP/Design-Kits/2010/fs0a_a//2010Q4v2.1/GENERIC_CORE/FrontEnd/synopsys/synthesis and the target library is fs0a_a/generic_core_ff1p32vm40c.lib. The verilog file is a accu.v (accumulator). I am using the gui interface but when i run the tcl file my gates are unmapped. What is wrong? Am I using wrong target library?
Thank in advance,
Konstan