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Hi frnds,
Can anybody tell me how we simulate netlist(gate level) file after doing rtl-gate level synthesis.
I m using cadence rtl compiler for synthesis of standard cells in verilog. After doing successful synthesis it generates gate level netlist which i have to simulate to verify the functionality of standard cells. Simulator is ncSim.
When i trying to simulate it shows error with all individual cells. And can't get that errors.
Looking for positive response from anyone.
Thanx.
Can anybody tell me how we simulate netlist(gate level) file after doing rtl-gate level synthesis.
I m using cadence rtl compiler for synthesis of standard cells in verilog. After doing successful synthesis it generates gate level netlist which i have to simulate to verify the functionality of standard cells. Simulator is ncSim.
When i trying to simulate it shows error with all individual cells. And can't get that errors.
Looking for positive response from anyone.
Thanx.