phutruan
Newbie level 5
- Joined
- Nov 18, 2014
- Messages
- 10
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1
- Activity points
- 81
Hi,
I have designed a purely combo logic circuit and for some reasons, I would like a path, for example, from point A to point B, to have a minimum delay.
So I did something like this "set_min_delay 0.5 -from A -to B"
After synthesizing the design, RTL compiler reports that the delay from point A to point B is unconstrained and less than 0.5.
There is no violations.
Could anyone help me ?
I have designed a purely combo logic circuit and for some reasons, I would like a path, for example, from point A to point B, to have a minimum delay.
So I did something like this "set_min_delay 0.5 -from A -to B"
After synthesizing the design, RTL compiler reports that the delay from point A to point B is unconstrained and less than 0.5.
There is no violations.
Could anyone help me ?