[SOLVED] RTL Compiler does not report timing violation on a path constrained by set_min_delay

[phutruan]

Hi,

I have designed a purely combo logic circuit and for some reasons, I would like a path, for example, from point A to point B, to have a minimum delay.
So I did something like this "set_min_delay 0.5 -from A -to B"
After synthesizing the design, RTL compiler reports that the delay from point A to point B is unconstrained and less than 0.5.
There is no violations.

Could anyone help me ?

 

[kornukhin]

set_min_delay is analog of hold constraint. RC doesn't fix any of hold constraints as it is require to build buffer tree, which will be further deleted by layout tool. Also timing information about required hold delay can be only valid during P&R.
But RC saves created constraints ad pass them to layout tool with wrtie_sdc command.