RTL Compiler: check_design command

Hi everybody,

I'm using rtl compiler 8.1 and i've elaborated my design on it. I got some issues in the summary. May you help me telling me what is important and what I don't need to worry about? I would really appreciate any help.

tks.

first switch to rtl compiler 10.1 if you can and secondly send your issues summary sothat we can see what the issues are really and help...

So, after the elaboration on both RTL Compiler versions and same rtl. I got these issues.
using 8.1:

Checking the design.

Check Design Report
--------------------

Summary
-------

Name Total
--------------------------------------
Unresolved References 0
Empty Modules 0
Unloaded Port(s) 0
Unloaded Sequential Pin(s) 8
Assigns 78
Undriven Port(s) 0
Undriven Leaf Pin(s) 0
Undriven hierarchical pin(s) 0
Multidriven Port(s) 0
Multidriven Leaf Pin(s) 0
Multidriven hierarchical Pin(s) 0
Constant Port(s) 0
Constant Leaf Pin(s) 2
Constant hierarchical Pin(s) 15217

Done Checking the design.


using 10.1:

Checking the design.

Check Design Report
--------------------

Summary
-------

Name Total
-------------------------------------------
Unresolved References 0
Empty Modules 0
Unloaded Port(s) 0
Unloaded Sequential Pin(s) 8
Assigns 102
Undriven Port(s) 0
Undriven Leaf Pin(s) 0
Undriven hierarchical pin(s) 0
Multidriven Port(s) 0
Multidriven Leaf Pin(s) 0
Multidriven hierarchical Pin(s) 0
Multidriven unloaded net(s) 0
Constant Port(s) 0
Constant Leaf Pin(s) 0
Constant hierarchical Pin(s) 18480
Preserved leaf instance(s) 0
Preserved hierarchical instance(s) 0
Libcells with no LEF cell 0
Physical (LEF) cells with no libcell 0

Done Checking the design.

unloaded sequential pins, constant hierarchical pins will go away after synthesis is done..It only means some flops are unused and when constant propagation is enabled from top , some hierarchical pins will have a constant value and so logic connected to those will be optimized...

Apart from these you have assigns and it only means you have assign statements which some P&R tools dont like and you can ask synthesis tool once done to write netlist wo assign statements ...

Overall you are good to go...

But after synthesis, the design still has unloaded pins. I've found pin blocks floating through the whole design, some blocks are clear from these issues, but others not. The problem is after synthesize -to_map command. I have extracted out the netlist, but the design functionality has been lost. After synthesize -to_generic is ok, I'm bothered with this step. Thanks a lot for the help!!! I was just wondering if all those issues (from check_design) would crash me in the next steps of synthesis.

This is my first big project and I'm really excited to finish it!

check if you have any sort of preserve attributes set on them ...

here im gonna post some lines of my script:

set_attr hdl_search_path /home/felipe/Desktop/r-vex_r38_MSc/r-VEX/synthesis/rtl/ /
set_attr lib_search_path $LIBRARY_PATH/
set_attr library $LIBRARY_PATH/liberty/c35_3.3V/c35_CORELIB.lib
#set_attr avoid true OAI212
#set_attr hdl_preserve_unused_registers true /
set_attr hdl_track_filename_row_col true /
set_attr information_level 9 /
#set_attr optimize_constant_0_flops false /
#set_attr optimize_constant_1_flops false /
#set_attr hdl_ff_keep_feedback false
#set_attr hdl_latch_auto_async_set_reset false is not valid
#set_attr hdl_max_loop_limit 1000
#set_attr hdl_undriven_net_value 0 is not valid

...
read design files
elaborate


I think i'm not using preserve attribute.

Add these and try again...
set_attr optimize_constant_0_flops true /
set_attr optimize_constant_1_flops true /
set_attr delete_unloaded_seqs true /
set_attr delete_unloaded_insts true /

Comment out set_attr hdl_track_filename_row_col true / <- This stores a lot of unnecessary information in the .g and db; turn this on only if/when debug is required

I'm going to home now. When i got there, i will do this and post the results. tank you!!

hello,im glad to know about this information.

Hi kbulusu, until the elaboration, the results are the same. Then I'm going to report you the read_sdc and read_vcd command issues I've gotten.

read_sdc command output:

read_sdc $CONSTRAINTS_PATH/rvex.sdc
Removing external delay 'create_clock_delay_domain_1_CLOCK_R_0'.
Info : Removed object. [TUI-58]
: Removed external_delay '/designs/system/timing/external_delays/create_clock_delay_domain_1_CLOCK_R_0'.
Removing external delay 'create_clock_delay_domain_1_CLOCK_F_0'.
Info : Removed object. [TUI-58]
: Removed external_delay '/designs/system/timing/external_delays/create_clock_delay_domain_1_CLOCK_F_0'.
Statistics for commands executed by read_sdc:
"all_inputs" - successful 1 , failed 0 (runtime 0.00)
"all_outputs" - successful 1 , failed 0 (runtime 0.00)
"create_clock" - successful 1 , failed 0 (runtime 0.00)
"get_clocks" - successful 2 , failed 0 (runtime 0.00)
"get_ports" - successful 2 , failed 0 (runtime 0.00)
"set_clock_transition" - successful 2 , failed 0 (runtime 0.00)
"set_clock_uncertainty" - successful 1 , failed 0 (runtime 0.00)
"set_input_delay" - successful 1 , failed 0 (runtime 1.00)
"set_output_delay" - successful 1 , failed 0 (runtime 0.00)
Total runtime 0

read vcd command:

read_vcd -activity_profile $VCD_PATH/rvex.vcd
Warning : Cannot set probability or toggle rate on a constant net. [TUI-92]
: Net 'instr[126]' is driven by a constant '0'.
...
this warning repeats for a long time, like this way...
....

Warning : Cannot set probability or toggle rate on a constant net. [TUI-92]
: Net 'instr[126]' is driven by a constant '0'.

Warning : Cannot set probability or toggle rate on a constant net. [TUI-92]
: Net 'instr[126]' is driven by a constant '0'.

Warning : Cannot set probability or toggle rate on a constant net. [TUI-92]
: Net 'instr[126]' is driven by a constant '0'.
.... until ....
Info : '-start_time', 'end_time' and '-time_window' options were not specified. [VCD-20]
: Time window will be set to the total simulation time in the VCD file.
: If no 'time_window' option is specified, the timing window is automatically selected based on power analysis effort level if the start and end times are also specified. Provide the start and end times with the '-start_time' and '-end_time' options respectively for the time window to be selected automatically based on power analysis effort level.


Setting end time as last timestamp in VCD file

Info : The '-vcd_module' option has not been specified with the 'read_vcd' command. [POPT-557]
: The first scope in the VCD file 'tb_system(test)' has been selected for processing.
: The first scope encountered in the VCD file has been selected for processing. This may result in lesser coverage if the selected scope does not match up to the design hierarchy to be annotated. To get better coverage, provide the VCD scope name with the '-vcd_module' option.
Done reading 10% of VCD file...
Done reading 20% of VCD file...
Done reading 30% of VCD file...
Done reading 40% of VCD file...
Done reading 50% of VCD file...
Done reading 60% of VCD file...
Done reading 70% of VCD file...
Done reading 80% of VCD file...
Done reading 90% of VCD file...
Done reading VCD file...

Info : The object could not be found under the specified hierarchy. [POPT-558]
: The instance 'system_0' could not be found under hierarchy '/designs/system'.
: This happens if the hierarchy specified with the '-vcd_module' option lies more than one level below the top level hierarchy or the hierarchy specified with the '-module' option. Adjust the specifications for the '-vcd_module' and the '-module' options to avoid this scenario.
Info : The object could not be found under the specified hierarchy. [POPT-558]
: The instance 'system_0' could not be found under hierarchy '/designs/system'.
Info : The object could not be found under the specified hierarchy. [POPT-558]
: The instance 'system_0' could not be found under hierarchy '/designs/system'.
Info : The object could not be found under the specified hierarchy. [POPT-558]
: The instance 'system_0' could not be found under hierarchy '/designs/system'.
Info : The object could not be found under the specified hierarchy. [POPT-558]
.... repeat... for a while...until...

Start of Activity Profile Generation

Doing analysis....
Info : The name of the generated SST2 database will have the VCD filename as its prefix as the '-write_sst2' option has not been specified. [POPT-560]
: Neither '-simvision' nor '-write_sst2' option has been specified.
: You have specified either the '-activity_profile' or the '-dynamic' option. To automatically load the SST2 database in the waveform viewer, you need to provide the '-simvision' option. To have your own named SST2 database, you need to use the '-write_sst2' option.

Completed analysis....

End of Activity Profile Generation

Warning : Cannot set probability or toggle rate on a constant net. [TUI-92]
: Net 'instr[126]' is driven by a constant '0'.
Warning : Cannot set probability or toggle rate on a constant net. [TUI-92]
... repeat..... till...
Warning : Cannot set probability or toggle rate on a constant net. [TUI-92]
: Net 'target_1[2]' is driven by a constant '0'.

These are the outputs of read_vcd and read_sdc. plenty of warnings...

---------- Post added at 15:23 ---------- Previous post was at 15:16 ----------

After build_rtl_power_models command:

build_rtl_power_models -clean_up_netlist -design $UNIT_NAME
Cleaning up the design /designs/system ...
Starting building RTL power analysis models ...
Preprocessing the netlist for building RTL power models ...
Building RTL power models for top-level design /designs/system ...
Building model 1xider ...
Building model 7xider ...
Building model 10xider ...
Building model 11xider ...
Building model 14xider ...
Building model 28xider ...
25% completed ...
Building model 47xider ...
Building model 82xider ...
Building model 89xider ...
Building model 98xider ...
Building model 111xider ...
50% completed ...
Building model 113xider ...
Building model 114xider ...
Building model 126xider ...
Building model 144xider ...
Building model 145xider ...
Building model 146xider ...
75% completed ...
Building model 147xider ...
Building model 162xider ...
Building model 178xider ...
Building model 181xider ...
Building model 200xider ...
100% completed ...
Done building models for power analysis.
RTL power modeling has finished. Use command 'report power' to see power report.

What the statement 200xider ... stands for??? I dont know what the "xider" means?

after synthesize -to_generic i ran check_design and..

Summary
-------

Name Total
--------------------------------------
Unresolved References 0
Empty Modules 0
Unloaded Port(s) 0
Unloaded Sequential Pin(s) 0
Assigns 231
Undriven Port(s) 0
Undriven Leaf Pin(s) 0
Undriven hierarchical pin(s) 0
Multidriven Port(s) 0
Multidriven Leaf Pin(s) 0
Multidriven hierarchical Pin(s) 0
Constant Port(s) 0
Constant Leaf Pin(s) 510
Constant hierarchical Pin(s) 724

Done Checking the design.

---------- Post added at 15:42 ---------- Previous post was at 15:23 ----------

After Synthesize to mapped...

check_design
Checking the design.

Check Design Report
--------------------

Summary
-------

Name Total
--------------------------------------
Unresolved References 0
Empty Modules 0
Unloaded Port(s) 0
Unloaded Sequential Pin(s) 0
Assigns 1011
Undriven Port(s) 0
Undriven Leaf Pin(s) 0
Undriven hierarchical pin(s) 0
Multidriven Port(s) 0
Multidriven Leaf Pin(s) 0
Multidriven hierarchical Pin(s) 0
Constant Port(s) 0
Constant Leaf Pin(s) 2
Constant hierarchical Pin(s) 917

Done Checking the design.

I will try the simulation with .sdf extracted out now after synthesis and report the results.

It does not work...
But, now with the netlist mapped, the simulation consider the time. I have set the timescale to 1ns/1ps, the clock testbench 1000 time units and SDC clock 100.

create_clock -name CLOCK -period 100.0 -waveform {50.0 100.0} [get_ports {clk}]

Are there any inconsistency clocks configurations on my settings?

200xider : That is just the internal name used for the sample generated while building the rtl models...it doesnt mean anything...
The attributes settings I gave you will only affect the synthesis commands like mapping, iopt (incremental optimizations ) etc...so wont have any effect on elaboration

now regarding your last post, I dont understand what you meant by it doesnt work..please elaborate what doest work...check_design clearly shows all unloaded seq objects/constant nets/pins etc are all optimized away...


so you have defined clock period to be 100ns with 50% duty cycle and you want to simulate the design for 1000ns and resolution is 1ns ...if this is what you intended, then yes you have defined it right...

Sorry for the uncleared post, and my English. Could you report if my English texts are clearly understandable? or comprehensible? I've just tried an elaboration, generic and to mapped synthesis, then I've also extracted the netlist from rtl compiler by write_hdl command and write_sdf for the standard delay format. I include the sdf statement in order to read sdf file and run the netlist timing simulation using the clock setting as I said before. I intended to set the clock in the testbench to be lower than the specified on my SDC file.

Your english is ok and I can understand most of the times..so dont worry about the language barriers....coming back to you qn, if you set clock slower, it might be ok..only if you make is faster, you might get failures since the ckt and delay extraction is characterized for period specified in sdc ...try synthesize -to_mapped -incr at the end ...

BTW, which company do you work for..PM me if you are ok with that...

Thank you kbulusu. Im from Brazil and I have been coursing the IC Brazil Program phase 3. OJB (on job training) at the UFMS (Federal University of Mato Grosso do Sul) We have the license for CAdence academic. I got the explanation about clock, tanks a lot. I need to get the rtl synthesis done, because we want to send the GDSII to the CMP france, the 1st round in september and 2nd round in october. My design is a VLIW processor called r-vex (r-vex -). I've prototyped on a fpga de2 and it worked fine. I just want to finish the logic synthesis. It's bothering me due the short deadline!! lol tanks man!

---------- Post added at 23:19 ---------- Previous post was at 21:59 ----------

After synthesize -incremental, the check design command has returned this:

check_design
Checking the design.

Check Design Report
--------------------

Summary
-------

Name Total
--------------------------------------
Unresolved References 0
Empty Modules 0
Unloaded Port(s) 0
Unloaded Sequential Pin(s) 0
Assigns 1011
Undriven Port(s) 0
Undriven Leaf Pin(s) 0
Undriven hierarchical pin(s) 0
Multidriven Port(s) 0
Multidriven Leaf Pin(s) 0
Multidriven hierarchical Pin(s) 0
Constant Port(s) 0
Constant Leaf Pin(s) 2
Constant hierarchical Pin(s) 917

Done Checking the design.

I have simulated the netlist but the results do not match with generic netlist. Lots of 'X' signals. Unstable signals behavior. I have already found this behavior in one netlist simulation I did, but only 'X' i found and i dont know how i solved thas.

Good to know about you and good luck with your training and project...

regarding you getting x, first make sure the synthesis tool did its job...so run formal verification between RTL and final netlist..if its passing, then your netlist is ok..it must be your constraints or issue with your simulation setup or testbench... synthesize -to_mapped -incr only does incremental optimization to give you a better structural netlist for you to do P&R....you can also run RCP which is synthesize -to_placed to see if your synthesis results are good enough in P&R..but anyways thats a different story...Cadence support website has new methodology kits calls RAK's and if you register for online account with them ( it might ask you for your cadence license server id etc to verify you are valid customer), you can download these methodology kits and these are very good to start and explore...

once again good luck...

Thank you man! I really have enjoyed your help. If you need something and, of course if I would be able to help you. Dont hesitate to request. Tanks.
Just for curiosity, where are you from and where you are?
tanks a lot.

Hi kbulusu nice discussion can you help me how we can say that, which attribute is suitable for our design.
because i saw that so many attributes but we use few of them