RTL and netlist formality mismatch problem.

Hi.
I'm trying to implement formality with RTL and netlist which is scan and clock gating inserted netlist.

When I trying to check formal between RTL and netlist(not clock gating and not scan insertion) then they are no mismatch.

But when I insterted scan and clock gating, then they are not equality. But I'm not sure what am I supposed to do ?

I just use these commends as following,
set_clock_gating_style - blar~blar -control_signal scan_enable

compile_ultra -gate_clock -scan ~blar ~blar

These are DC commands. They will not help you.
There are some switches in Formality which you have to use to tell the tool that it is a clock gating inserted netlist. Search it in the formality doc and use them..

Thanks but I can't find it. Would you please help me?
I just found the command set verification-clock_gate_hold_mode low.
But I have still problems what mismatch.

I get it.
TE and EN should have to be set 0 to constance value.

- - - Updated - - -

sharath666 said:

These are DC commands. They will not help you.
There are some switches in Formality which you have to use to tell the tool that it is a clock gating inserted netlist. Search it in the formality doc and use them..

Click to expand...

Thanks Sir, I have some query.
my RTL logic has en port which is clock gating enable port.
Then I have just compiled with following commends
set_clock_gating_style - blar~blar -control_signal scan_enable*
compile_ultra -gate_clock -scan ~blar ~blar
then I can found some scan DFF and clock gating latch inserted to netlist.

here is some question.
Which one I have to set to constance value 0 or 1. At reference's en port?
Or at implementation's TE and EN? Which one I have to set?

Another one question is what if I handle 100M gates logic design, then how do I set all register?

If the RTL has a clock gating en port, does it mean you are doing clock gating in RTL? Or is the synth tool doing the clock gating for you?

sharath666 said:

If the RTL has a clock gating en port, does it mean you are doing clock gating in RTL? Or is the synth tool doing the clock gating for you?

Click to expand...

Good question. let me see my code
Look.



module adder(*
en,*
clk ,*
reset_n,*
i_a,*
i_b,*
o_out*
);*

input clk,en;*
input reset_n;*
input i_a;*
input i_b;*
output [3:0] o_out;*

reg [3:0] o_out;*



always @(posedge clk or negedge reset_n)*

begin*
if(!reset_n)*
o_out < = 0;*
else*
if (en )*
o_out < = i_a + i_b ;*
end*
endmodule*





You can see that the en is used both. RTL and netlist.

This is not clock gating. This is just a mux before a flop. So the synthesis tool must be doing the clock gating.So that en is not doing what you think it is doing. So you should not drive this en from synthesis point of view. If I am right, TE should be driven low during synthesis(it is some scan stuff)

sharath666 said:

This is not clock gating. This is just a mux before a flop. So the synthesis tool must be doing the clock gating.So that en is not doing what you think it is doing. So you should not drive this en from synthesis point of view. If I am right, TE should be driven low during synthesis(it is some scan stuff)

Click to expand...

Thanks . Is this not clock gating? Apparently, I checked clock gating report. The report said, clock gated 100%.

Q1.So what is the clock gating? Would you please let me know some example?

Q2. Also did you mean that I don't need to set en to 0 in formality? Actually, I want to know which one (RTL or netlist or both) I should have to be taken 1 or 0 at formality. You know that the TE is just only in netlist not RTL. Also clock gating enable signal is in RTL and netlist. So I confused that what if I equivalent check between scan and clock gating insertion netlist and RTL, which one should I have to set 0 or 1 in formalify? RTL or netlist or both?

Q1. You can search "clock gating cells" in Google. You will get some images as search results. That is what is clock gating. You can run a synthesis for your code and see the corresponding schematic. You will notice the difference.
Q2.You will need to set TE of netlist to 0 in formality run.