[SOLVED] RS-232 port and XUPV5 LX110T evaluation platform (Xilinx)

[isamel85]

Hello,

In fact, I worked with XUPV5-LX110T evaluation platform (Xilinx).
Indeed, I tried to send a data from Matlab script (communication protocol) on the RS-232 serial port, where:

- I use the RS-232 Null Modem (DB9) Female-Female between the computer and the platform;

- The data sent is 8 bits comply with the standard;

- The serial port (on the platform) is interfaced with the FPGA by referring to XUPV5-LX110T user constraints file .ucf (RXD0 - RXD7) (the UART module is already on the platform)

Control pins
NET PHY_COL LOC="B32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET PHY_CRS LOC="E34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET PHY_INT LOC="H20"; # Bank 3, Vcco=2.5V, No DCI
NET PHY_MDC LOC="H19"; # Bank 3, Vcco=2.5V, No DCI
NET PHY_MDIO LOC="H13"; # Bank 3, Vcco=2.5V, No DCI
NET PHY_RESET LOC="J14"; # Bank 3, Vcco=2.5V, No DCI
NET PHY_RXCLK LOC="H17"; # Bank 3, Vcco=2.5V, No DCI
NET PHY_RXCTL_RXDV LOC="E32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET PHY_RXER LOC="E33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20

Data pins
NET PHY_RXD0 LOC="A33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET PHY_RXD1 LOC="B33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET PHY_RXD2 LOC="C33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET PHY_RXD3 LOC="C32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET PHY_RXD4 LOC="D32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET PHY_RXD5 LOC="C34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET PHY_RXD6 LOC="D34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET PHY_RXD7 LOC="F33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20

- The FPGA is connected only to the TX and RX data pins on the serial port (by referring to the manual);

- I checked that I’m getting expected data at serial port of my machine properly by doing the loopback, I send and receive the same data. I use RealTerm to send and capture data on the port (For the Baudrate, when I set it at 9600, the communication works fine according that I had as boot loading the platform (bootloader menu) using RealTerm).

- I implemented a VHDL description that is used to link the pins RXD0--RXD7 with GPIO_LED_0--GPIO_LED_7 respectively in order to check if I have the same data (sent and received) and I downloaded the Bit stream configuration file .bit (I verified my VHDL description in ModelSim by making a testBench; it works fine).

NET GPIO_LED_0 LOC="H18"; # Bank 3, Vcco=2.5V, No DCI
NET GPIO_LED_1 LOC="L18"; # Bank 3, Vcco=2.5V, No DCI
NET GPIO_LED_2 LOC="G15"; # Bank 3, Vcco=2.5V, No DCI
NET GPIO_LED_3 LOC="AD26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET GPIO_LED_4 LOC="G16"; # Bank 3, Vcco=2.5V, No DCI
NET GPIO_LED_5 LOC="AD25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET GPIO_LED_6 LOC="AD24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET GPIO_LED_7 LOC="AE24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors

I started to send a data using Matlab Script (given that Matlab returns no problem in the command window), but there is no change on the LEDs.

I want to know if I need to instantiate the control pins of the port in my VHDL description (eg PHY_RXCLK may be it requires a clock to operate the UART Module)? or I can use just the RXD0—RXD7?

Please can someone help me to solve this problem?

Thanks in advance for any help.

Best regards,
Isamel

 

[ads-ee]

You've posted a bunch of pin locations but what about the source code that shows how you implemented the design.

Without you VHDL code it's hard to say what you are doing on the FPGA side. But given a name like PHY_RXCLK, I would suspect you need to drive it with a clock to get the UART to output the received data.

 

[mrflibble]

Make a small FSM that outputs a sequence of test characters on the TX going out of the fpga. Then use an oscilloscope to see if the signal on that TX pin looks like you think it should. As in correct voltage levels and correct timings.

If you made a mistake in the UCF this will show up. If you made a mistake in the baud rate generator this will show up.