I wonder about the stack up:
-- Signal - Top
-- Vcc
-- GND
-- Signal - Bottom
It is typically:
-- Signal - Top
-- GND
-- Vcc
-- Signal - Bottom
Assumptions:
1.) Lines that are sensitive, differential, or that require impedance control generally do not have vias if they can be avoided. This means they are on the top layer with the components.
2.) The width of the line and the height from the ground plane (w/h) determine impedance for a given dielectric such as FR-4.
3.) It is important a ground plane not have any breaks or gaps under any signal lines so it tends to be a plane layer.
4.) The Vcc, or power layer, tends to be a routing layer as opposed to a plane. This supports a star routing of power if needed, different power buses, and "keep out" areas where EMI coupling to power may be an issue such as under crystals, Ethernet transformers, and switching regulators.
If the ground is layer 2 the height (h in w/h) is better controlled since it is a single layer of pre-preg or core, and unlike the Vcc which would be layer 3, it does not have routed lines or cutouts bisecting layer 1 lines.
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In your case however (12MHz), signal integrity isn't an issue I'd worry about too much.
It becomes VERY important in high speed design.
The crystal is 12MHz but what is the processor speed? Our ARM has a 16 MHz crystal but operates at a 80MHz clock and this is doubled in a FPGA using DCM to 160MHz for a memory interface.