Routing signals on the inner layer under crystal oscillator or switching regulator

[nelsonys]

I have a board space constraint with my current PCB. I am thinking of routing some signals under the crystal oscillator and switching regulator on the inner layer. I was wondering how severe will the effect be?

As far as I've learnt, noise coming out from crystal oscillator and switching regulator is well-coupled to the 2nd layer of the ground plane, so I guess it might not pose any adverse effect to the signal traces.

Folks, what do you think?

 

[abhi002]

if there is solid plane underneath crystal,u can do routing in inner layer.

for me ,no issues

 

[senilicus]

As long as there is a solid (ground)plane between the signals and the Oscillator/Regulator it should not be a problem.

 

[marce]

Agree, plane underneath will terminate the h and e fields. Some capacitive coupling may occur.
CAVEAT, I would not run tracks under a switching regulators switching nodes... It is just a rule I live by and insist on, due to the hi dI/dt switching. It may be overkill but it is a rule I follow.

 

[abhi002]

only thing is we should know this and try to avoid it.

if not possible in any circumstances,then go ahead dude

 

[nelsonys]

Marce,

Any documents to support this? Circuit designers need proofs for this...

 

[marce]

Yes Nelsonys,
Basic electronics mate, high switching currents bigger problems, 25 years plus doing this job and research, the fact that I do mil and areo designs so my EMC testing is more stringent than comercialso I have seen problems, a desire to do a design to the BEST of my abbilities. and be less abrupt please.
I have had had training on sirte provided by Nation Semiconductor on the layout of switch mode power supplies and the EMC problems they cause, provided by thier . We dont run any copper (including ground tracks) under any switching nodes.
The CE club have lots of notes on switching circuits and noise, in fact Keith Armstrong has a new series that has been running for 3 months.
EMC Information Centre - The EMC Journal (Free in the UK)
Henry Ott, Electromagnetic Compatability Engineering
And quite honestly only a complete novice would run a signal under a switching node unless there was no other alternative.
In the past I have provided many links and references, in this instance I am rather disapointed by the question, having seen the problems caused by noise from switching nodes, so I would reccomend you go learn.

THIS IS REFERENCING MY COMMENT ON SWITCHING NODES NOT CRYSTALS.

 

[nelsonys]

Marce,

Yes I have rules for not routing any signals under switching power supply, but for prototype version, we are constrained so much by the board size set by the circuit designer. And this is one of the communication gap between them.
Besides, I'm quite confused with we don't any ground tracks under any switching nodes.
Ground that is not related to the switching regulator?

Besides EMC consideration, I do have issues about thermal relief about the National Semiconductor Simple Switcher LMZ14203 (2A)
Would you mind to share how do you pour your ground on the top and bottom layer?
For my case, I choose inner layer 2 for a complete ground plane, therefore I don't connect ground pour on the top and bottom layer of the simple switcher with to other circuits in order to direct the ground return straight back to the 2nd layer ground plane. What is your comment on this?
My colleague insisted me to connect all of them no matter where is it, in order to cater for sufficient thermal relief.

 

[marce]

We have been playing with the simple switchers, I'll dig into my notes. Basilcly I like these as they cut down the switching loop, when you have an external inductor. It is this large loop with high switcing currents that is our biggest concern, so the simple switchers look like an excellent solution. Initial tests have been promising.

 

[marce]

Hi Nelsonsys,
sorry for the delay, had a busy afternoon.
For the simple switchers I used I did the layout based on the examples shown in this guide:
**broken link removed**
I use thermal vias with a finished hole size after plating of 0.25mm. Most of the boards I do have numerous ground planes, so have quite good thermal properties, but on lower layer count boards i strive to leave as much exposed copper on the opposite side of the device to provide an area to radiate heat away from the device. The other advantage of adding the thermal vias is that it creates a keep out area, so it stops you routing traces under the device. I also use a thermal camera extensively with boards as it gives an instant indication of hot spots and possible thermal issues. Thermal engineering is like signal integrity becoming another skill set we are going to have to cope with as PCB designers, the thermal Camera is a gods send in helping sort these issues.
**broken link removed**