Junus2012
Advanced Member level 5
Hello
For my design of memory based on flip-flops, I am using the digital cells from the foundry and I am facing an issue that I can not avoid routing over active regions of transistors because the design has little complicated control circuit that access the cells in different positions, so not possible to always grantee to avoid routing over transistors.
However I am routing using higher metal layers that is MET2 and MET3.
I tried to keep routing besides the cells not over it but that led to large layout area.
From my knoweldge in analog layout routing over active region should be avoided in order to have symmetrical stress for matching purposes, but in digital design routing should not be a problem as we dont have to wary about matching, but still I am not sure and I would like to discuss this issue with you
Thank you in advance
Regards
For my design of memory based on flip-flops, I am using the digital cells from the foundry and I am facing an issue that I can not avoid routing over active regions of transistors because the design has little complicated control circuit that access the cells in different positions, so not possible to always grantee to avoid routing over transistors.
However I am routing using higher metal layers that is MET2 and MET3.
I tried to keep routing besides the cells not over it but that led to large layout area.
From my knoweldge in analog layout routing over active region should be avoided in order to have symmetrical stress for matching purposes, but in digital design routing should not be a problem as we dont have to wary about matching, but still I am not sure and I would like to discuss this issue with you
Thank you in advance
Regards