ROM memory use in modelsim simulation

HI....
I have generated ROM block with help of xilinx 12.1 and i have initialized the ROM/RAM block with some values (tried for both blocks)
.... but when i simulating this one with help of MODELSIM but it was not simultating giving as error :
Loading work.blk_mem_gen_v4_1(blk_mem_gen_v4_1_a)
# ** Error: (vsim-3732) D:/programm/bchdecoder_syndrome.vhd(74): No default binding for component at 'modulea'.
# (Port 'dina' is not on the entity.)
# Region: /bchdecoder_syndrome_t/dut/modulea
# ** Error: (vsim-3732) D:/programm/bchdecoder_syndrome.vhd(74): No default binding for component at 'modulea'.
# (Port 'wea' is not on the entity.)
# Region: /bchdecoder_syndrome_t/dut/modulea
# Loading xilinxcorelib.blk_mem_gen_v4_1(behavioral)
# Loading ieee.std_logic_textio(body)
# Loading xilinxcorelib.blk_mem_gen_v4_1_mem_module(mem_module_behavioral)
# ** Note: Block Memory Generator CORE Generator module loading initial data...
# Time: 0 ps Iteration: 0 Instance: /bchdecoder_syndrome_t/dut/modulea/u0/mem_module
# ** Error: (vsim-7) Failed to open VHDL file "blk_mem_gen_v4_1.mif" in rb mode.
# No such file or directory. (errno = ENOENT)
# Time: 0 ps Iteration: 0 Instance: /bchdecoder_syndrome_t/dut/modulea/u0/mem_module
# ** Fatal: (vsim-7) Failed to open VHDL file "blk_mem_gen_v4_1.mif" in rb mode.
# No such file or directory. (errno = ENOENT)
# Time: 0 ps Iteration: 0 Process: /bchdecoder_syndrome_t/dut/modulea/u0/mem_module/line__1466 File: D:/xilinx12.1/ISE_DS/ISE/vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V4_1.vhd
# FATAL ERROR while loading design
# Error loading design

Plz help in this problem

it sounds like you havent included the source code for your modulea in the project.

ya i have added all file in project....
plz can u tell source file extension..

Actually, it looks like if you have copied the component wrong, or you have re-generated the core since you last updated the component.