rajavel.rv
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Hi all,
I have a polynomial equation of CRC(cyclic redundancy check) for ROHC compression and decompression technique, the polynomial equation equation is shown below,
CRC 3-BIT : C(x) = 1 + x + x^3
CRC 7-BIT : C(x) = 1 + x + x^2 + x^3 + x^6 + x^7
CRC 8-BIT : C(x) = 1 + x + x^2 + x^8
Here, the problem is how can i write code for verilog HDL using this polonimal, what is input and input sizes, but the output is CRC3 = 3bit, CRC7 = 7bit, CRC8 = 8bit.
note : RFC Document of ROHC implementation not having a clear details for this CRC technique.
Anybody have a idea please give me a suggestion and send the link details.
Thanks Advance,
Best Regards,
Rajavel Ashokraj
I have a polynomial equation of CRC(cyclic redundancy check) for ROHC compression and decompression technique, the polynomial equation equation is shown below,
CRC 3-BIT : C(x) = 1 + x + x^3
CRC 7-BIT : C(x) = 1 + x + x^2 + x^3 + x^6 + x^7
CRC 8-BIT : C(x) = 1 + x + x^2 + x^8
Here, the problem is how can i write code for verilog HDL using this polonimal, what is input and input sizes, but the output is CRC3 = 3bit, CRC7 = 7bit, CRC8 = 8bit.
note : RFC Document of ROHC implementation not having a clear details for this CRC technique.
Anybody have a idea please give me a suggestion and send the link details.
Thanks Advance,
Best Regards,
Rajavel Ashokraj