Rise time and frequency scaling

[tasctasc]

Just wondering how rise time scales with technology now that the frequencies are held approximately constant with the move to multi-core? Intuitively the transistors should still be faster since L is smaller so the rise time should get smaller. However, if the clock frequency doesn't change and typically the rise time is designed to be ~10% of the clock frequency then are the transistors made intentionally slower? If so, is this done by using larger L's? Doesn't that at least partially defeat the purpose of the scaling?

 

[AmrZohny]

Rise time is a function in both Ron of the transistor as well as CL

As the technology scales, the parasitic capacitance of the inverter (basic digital block for eg.) goes down.

**broken link removed**

However, the on-resistance does not scale on the same ladder....

RON = 1/(µnCOX W/L)(VGS − VT)

Combined ... you can adjust for the required tPHL and tPLH ... but in general ... the minimum value is always used to realize the digital blocks unless there is a fanout problem ... in analog design ... well .. it is another story = )

https://www.fairchildsemi.com/ms/MS/MS-556.pdf

 

[tasctasc]

Thank you AmrZohny for the information. Is the minimum value still always used for digital blocks in multi-core processors running at relatively slow frequencies?