[SOLVED] RISC-V Register File

[michaelScott]

Hello friends,
I am designing a register file which is compatible with RISC-V ISA definitions. But as seen on the simulation result register does not read the data input despite the RTL schematic shows no problem.
Can you help me about that.
Thanks in advance.
the codes:
https://github.com/hakanxdurak/RISCV-RegisterFile

 

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You don't have the W port in the instantiated module in your testbench.

Warnings when the modules are linked during the loading of the simulation need to be fixed, not ignored.

The warning is probably something along the lines of "Instantiated module xxxx has N-1 ports expected N."

 

[michaelScott]

You don't have the W port in the instantiated module in your testbench.

Warnings when the modules are linked during the loading of the simulation need to be fixed, not ignored.

The warning is probably something along the lines of "Instantiated module xxxx has N-1 ports expected N."

thanks. i was careless i did not notice