Ring Oscillator with std-cell

[fiber7]

Hi everybody.

We are currently using MOSIS IBM 0.13um with Artisan std-cell libs (Digital FLow).

In our design we need to insert a Clock source, but we don't have the time and the skill to design a PLL.

What we would like to do is to design a Ring Oscillator using std-cell inverters.
I know that this solution is far to be stable, but for us it would be enough to have a *a kind of* clock.

I would like to know your opinion about that, and possibly, all the tips to succeed in this task.

Thank you!

Fib

 

[Fom]

You can use DELAY cells (usually this Standard Cell is included in the most libraries) and one inverter.
After that add divider by 2 to get duty ratio 50%.

 

[fiber7]

Thank you Fom!

Do you think I should treat the ring oscillator like an *analog* block, i.e. creating power rings around this block like it is supposed to be for real analog blocks?

Cheers.

Fib

 

[Fom]

No need. Treat that as pure digital.

 

[laglead]

Hi everybody.

We are currently using MOSIS IBM 0.13um with Artisan std-cell libs (Digital FLow).

In our design we need to insert a Clock source, but we don't have the time and the skill to design a PLL.

What we would like to do is to design a Ring Oscillator using std-cell inverters.
I know that this solution is far to be stable, but for us it would be enough to have a *a kind of* clock.

I would like to know your opinion about that, and possibly, all the tips to succeed in this task.

Thank you!

Fib

Hi,
Great jitter may corrupt your function. Then you cannot check the design. So, what is your purpose to have this kind of clock?
If you have to do this, please add many decoupling caps as possible around this oscillator.

 

[bill_sun]

this lies on the performance of osc. its so simple to design a oscillator with delaycells .but we can confirm that its not a good osc with low jitter.