Ring Oscillator VCO design

ring oscillator vco

I am desiging a 400MHz Fully differential Ring oscillator design .The output voltage swing is varying with in the tuninig range .Can any one suggest how to control the output swing ? .Secondly do I need to use a comparator to convert the sine wave VCO output to a square wave and limit the amlpitude as well .Can any one suggest better techniques .

ring oscillator sine wave

what's the structure oof the ring oscillator?
maybe you can use level shifter to shift the output to full swing.


you can also use DFF to make the vco output square wave.

cmos ring oscillator vcos

Basically, it is difficult to suggest a way to control the output amplitude without knowing the structure of you delay cell in the VCO. Having an amplitude not dependent on the tuning is a good idea since it makes the transfer characteristic of the VCO more linear. Are you using something like Maneatis ring oscillator?
As for converting the sin wave to sqare wave - it is my opinion that you should have the waveforms of the ring oscillator as close to sqare as possible - this means that your cells are fast enough and that all transient processes have more or less settled - hence you are less prone to uncertainties and jitter. If your ring oscillator can not produce something close to sqare wave, think about reducing the amplitude, then it will have enough time to settle. What technology do you use?
Second, you don't take the signal from the ring oscillator directly. You use some sort of a buffer - which will also be responsible for converting your reduced swing to full CMOS output. This is a kind of comparator and it also isolates the ring from the outside world.

sqare vave oscilator

It is hard to control the VCO output swing in different tunning range.
I suggest you add the compartor in the vco output so that let the VCO output SR high and increase the vco output amplitude, it will have better jitter performence.

sine wave added ring oscillator

huanchou said:

It is hard to control the VCO output swing in different tunning range.
I suggest you add the compartor in the vco output so that let the VCO output SR high and increase the vco output amplitude, it will have better jitter performence.

Click to expand...

I think so too. But remember to control the DC operating point so that
the comparator can work. Please see Maneatis' classic paper on PLL and DLL.

By the way, I dont think that this comparator could help the jitter performance.
This could be derived by Weigandt's thesis.

weigandt thesis

this paper may be helpful to you
"A PLL Clock Generator with 5 to 110Mhz of Lock Range for Microprocessors"
JSSC NOVEMBER 1992