ring counter using d flipflop

I am trying t make ring counter in cadence virtuoso using d flipflop.I need to know wht should we do with unconnected pins like clr pin of first flip flop and set pins of rest flipflop.
<a title="ringcounter.png" href="http://obrazki.elektroda.pl/6539339700_1363354309.png"><img src="http://obrazki.elektroda.pl/6539339700_1363354309_thumb.jpg" alt="ringcounter.png" /></a>

ece04 said:

wht should we do with unconnected pins like clr pin of first flip flop and set pins of rest flipflop.

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Connect them all to +VDD .

thank you for reply.I have one more question what should i give as input to reset and clr .I was giving input vdc with 2v and input for vdd is 2.5 v.Is it ok?

ece04 said:

... vdd is 2.5 v.Is it ok?

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Yes, that's ok!

input to clr should be pulse or constant voltage?I mean vpulse or vdc?

ece04 said:

input to clr should be pulse or constant voltage?I mean vpulse or vdc?

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Constant voltage, you don't need a vdc source, simply connect them to VDD, like all unused inputs of this ring-counter. That's the inactive state, the overbar means the active state is "0" or GND=VSS, which never will be used for unconnected inputs.

The start is initialized by the (negativ going) INIT pulse, which PResets the first output to a logic "1" and CLeaRs the others to a logic "0".

A ring counter wants a particular initial load-value or
you can get spurious states especially in very long
ones. I'd recommend using FFs with both set and clear,
tying (say) all but bit 0 resets to a common reset and
the sets inactive, and bit 0 opposite (getting a single
marching-one) or doing this by using N-1 reset-only
'flops and one set-only (this ought to give you better
results when you get to the fault-coverage design
analysis, where tied-off inputs are "untestable").

What you don't want, is multiple "ones" marching so
sparsely that the feedback logic (if any) doesn't
"see" how filthy the pipe is and can't correct it back
to whatever the desired "load" is.

You could also do this without set or reset, using a
data mux scheme. This could make your reset synchronous
(generally a good idea) and ensure that the ring is always
loaded back to initial on count=0 edge (reset being now
a second term in the feedback event).