Hello everyone, I am simulating an RF power detector (RMS power detector followed by a cascaded logarithmic amplifier). I want to reduce the offset from the cascaded logarithmic amplifier, so I used the chopper technique. However, how can I account for the effect of the clock on the switches when I run harmonic balance?
Include the harmonics of the clock signal in your harmonic balance analysis. The clock signal generates harmonics that can interact with your RF signal.