Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

RF power amplifier optimum load

Status
Not open for further replies.

adnan012

Advanced Member level 1
Advanced Member level 1
Joined
Oct 6, 2006
Messages
468
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,298
Activity points
4,923
hi,
i am confused in finding the optimum load impedance for SD57060.

As shown on SD57060 LOAD IMPEDANCE.JPG (taken from SD57060 DATASHEET)
at 945MHz the ZL is 1.6+j*0.25

on book.JPG
there is a formula to determine load impedance.

on sparameters.JPG (taken from SD57060 DATASHEET)

VDD = 28V
IDS = 2A
S22 = 0.978 -168.77

This gives zout=50*((1+polar(0.978,-168))/(1-polar(0.978,-168))) //equation in ADS

Zout = 14ohm

if the formula is correct.

why this information is given with VDD and ids? does it follows the Ropt=(Vdgb-|Vp|-Vk)/IDSS formula for class AB AMPLIFIER along with class A amplifier.

What is the actual optimum load for SD57060?
What is Zl as show on SD57060 LOAD IMPEDANCE.JPG?
Why ADS LSSP shows s22 1.6+j*0.25 at 945MHz?
Which value should be used for LOAD PULL TEST?
 

Attachments

  • book.JPG
    book.JPG
    72.3 KB · Views: 173
  • SD57060 LOAD IMPEDANCE.JPG
    SD57060 LOAD IMPEDANCE.JPG
    53.5 KB · Views: 164
  • sparameters.JPG
    sparameters.JPG
    188.2 KB · Views: 152

The Data Sheet is telling you what is the load needed to get max Pout.
The Book info is for a MESFET, but this is a LDMOS Fet.
A Load Pull test is to tell you what a DUT will do under various types of loads, and
what type of performances you can expect from the DUT. It Sweeps the Output
load.
 
Last edited:

thanks for reply.

Phillips application note

100 − 450 MHz 250 W Power
Amplifier with the BLF548 MOSFET

Also use the same technique.

Rload = Vds^2/2P
and then compensate the output capacitence
 

hi,
what is the difference between two impedance
First which is given at SD57060 LOAD IMPEDANCE.JPG
at 945MHz the ZL is 1.6+j*0.25

Second on sparameters.JPG

VDD = 28V
IDS = 2A
S22 = 0.978 -168.77
 

I suggest, u should utilize the Load pull tool of ADS... replace the default transistor with your transistor model.... enter 945 MHz frequency... n simulate.. it will give different values of impedance's along with efficiency n other parameters.. chose the one that has good eff. n can easily be matched to 50 ohm...
 
Optimum Load Impedance is different than S22,therefore you find somehow different.
This load impedance is "measured" under large signal condition but s-parameters are measured under only low signal driven conditions.
They are not same at all..
 
BigBoss, I may sound naive but what the difference the magnitude of signal level will cause to impedance... won't it remain constant under all conditions???
 
BigBoss, I may sound naive but what the difference the magnitude of signal level will cause to impedance... won't it remain constant under all conditions???
Eventough there isn't any fixed definition about "large signal condition" for a measurement, operating point of an active/passive system is assumed "fixed" during s-parameter measurements by definition so that s-parameters are small signal parameters like z,y parameters.In additional to this, large signal s-parameters are also exisiting and finally X-parameters by Agilent have recently been introduced to caracterize the active components.
All of them generally assume the the operating point is defined and not changed during measurements.
But if a system is driven a large signal, operating point is not fixed anymore-for instance auto-polarization effect in power amplifiers-that's why these parameters shouldn't be confused between them.Relatively large voltage/current swings will change the OP.
 
hi,

Thanks for reply. I am facing another issue with SD57060 DC analysis, using its ADS MODEL. The Drain current keeps on increasing constantly with the increase of Vgs without any saturation point. I think there is an issue with Rd and Rs value as shown in the figures. The values set for mos_k60_28c is 0.1 ohm for both RD and RS. However 0 Ohm set for jf_k60_28c jfet. What is the method of finding correct values of these parameters.By changing rd and rs to 0.2 Ohm for jf_k60_28c jfet the current saturation point is achieved. as shown in figure 5.
 

Attachments

  • 1.JPG
    1.JPG
    107.8 KB · Views: 155
  • 2.JPG
    2.JPG
    110.6 KB · Views: 147
  • 3.JPG
    3.JPG
    110.2 KB · Views: 136
  • 4.JPG
    4.JPG
    53.6 KB · Views: 150
  • saturation.JPG
    saturation.JPG
    50.4 KB · Views: 146

In JFET MODEL , RD play a major role in Id saturation ( rd comes in parallel in the model), hence proper characterization of the device will determine the value, in specific bias region Rd will change but for the linear region rd remains constant by changing the value we can get the current compression but that will come to specific bias only.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top