RF output power vs Frequency

Hi all,
I have a basic question about RF output power of an transistor. I have transistor able to deliver 100W at 1GHz. I tried to re-optimize matching network to make it work at 2 Ghz. The power gain is going down ~4 dB and RF output power also go down. I am not sure it's due to my matching network not optimized or there is some therotical limit for higher frequency? I know gain will go down, but why power :?: ? What's the physics behind it? Thanks in advance for any kindly reply.

Have you tried raising the drive level? Does the device data sheet claim it works at the higher frequency? Are you using the source and load impedance the data sheet indicates for the higher frequency?

In general, there is a transit time across the active region of transistors and velocity limits of charge carriers.

This is not exactly like slew rate limits in op amps, but can be used as an imagination method in thinking of the output voltage and current not reaching the limits before the end of the sine wave quarter cycle time.

Power amplifiers are very interesting circuits.
There is always constraint points that limits the circuits. It's called as "Fano Limits" and depend on many parasitic and behavioural and physical devices in the semiconductors.

Most probably the model which has been used to simulate the transistor is no longer valid at 2GHz. And therefore you might made a mistake..

Another thing , if you did a impedance matching circuit that will work "conjugate of output impedance" that is completely wrong. Because high power amplifiers never work at conjugate matching conditions at high power leveles. Instead , they work at "optimum output impedance" range. Therefore you have to find either analytically or aid of measurements a point of impedance that will provide maximum power.

Other one , operating point should be very well defined so that optimum power could be available.

Last , in the transistor especially Ccb , Csc Cbe capacitances may be very high , therefore under the high voltage operating conditions , they behave worse than lower power. It's very clear.
dVc
Ic=----- ( Capacitances have been assumed constant however never
dt
become)

Collector resistance resistance increase with high power because Vcb is also increased ( base depletion region decreases ) and therefore transition from emitter-to-collector becomes more resistive.

I hope this helps..

Thanks for your replies. It's very helpful. I am working on a LDMOS type transistor. And I did power match on the output instead of conjugate matching. I am not sure whether I didn't it really right or not. I get much less power at 2Ghz than 1Ghz, ~70%. How do I know I reached the optimum point already? That's why I ask about the theritical limit of frequency dependence. Any suggestions?

Have you done a power sweep vs input power vs freq? You'll be able to see much more details from these plots.
Do you have a wide gain flatness corresponding to -4dB drop until compression? Or is the -4dB drop taken at compression? It could be the case where it is already in compression by a few dBs....