RF MOS Gate Capacitance

[cobaltblue1219]

I'm running an SP simulation on a GaN HEMT, and am using Y parameters to estimate CGS CGD CDS and so on.

During the initial simulations without stabilization added, I get a CGS of 9pF

After I add the stabilization circuit, the CGS falls to 1 to 2 PF.

The stabilization circuit comprises of a 20ohm resistance in parallel to a 0.5 p cap, placed in series to the gate terminal of the device.

Could someone explain what are the drawbacks of using this type of stabilization at the input to reduce cgs?

Thank You!!!

 

[vfone]

Drawbacks could be reducing gain and reducing bandwidth.
Also, increase of power consumption and sensitivity to temperature variations should be taken into consideration.