RF CMOS layout tips and techniques

[calculus_cuthbert]

Hi,

I am starting a layout for a LC CMOS VCO and a few more blocks in the GHz range. I would really appreciate it if someone could give me RF layout tips and techniques and what I should keep in mind.. Also if there is a reference or guide/tutorial for RF layout that would be very helpful

Thanks.

Added after 5 hours 17 minutes:

I also had a question regarding the layout of an accumulation capacitor. How do I reduce the gate resistance of an accumulation capacitor?

For an LC VCO, the MOS capacitor (varactor) should be matched, so should I go with common centroid configuration??

 

[Pat_Mustard]

rf cmos capacitor

- Use the metal with lowest capacitance to substrate (usually top metal but not always, check design manual) for signal tracks

- Try and keep parasitic resistance to a minimum by using low sheet RHO metal and keeping tracks short. This is of course where it gets tricky as you are unlikely to want circuitry anywhere near an inductor and so will be forced to route 50um or so, and to keep sheet resistance low wide tracks are attractive, but this will increase your parasitic capacitance. Speak to your designer, ask the maximum values of parasitc R and C he can tolerate and work them out.

- Diff pairs, current mirrors etc are likely to have tight matching requirements so use dummys, cross quading etc.

- Consider having gnd shields between your RF signals and substrate, and often, between each other. Again speak to your designer, often they will not want any additional capacitance on the signal, other times they will be terrified about signals coupling into substrate and being picked up at mixer i/ps, LNA etc

 

[calculus_cuthbert]

cmos layout parasitics for rf

Thank you for your suggestions. Actually I have designed the VCO.

This is my first RF design so am not too familiar with RF techniques. To have an idea of how much parasitic capacitance I can tolerate what approach should I take?

About the gnd shields how do I put ground shields?

I also had a question regarding accumulation capacitors and MOS varactors.

In my design I have used MOS varactors and a fixed accumulation capacitor in parallel. But am not sure how I should distribute the capacitance. Whether I should size the MOS varactor up for more capacitance or the accumulation capacitor for more capacitance. For me tuning is not that important. So in terms of parasitic capacitance that would affect the frequency and also the series resistance that would affect the quality factor which one would be less harmful??

Thanks a lot!

 

[oermens]

cmos layout capacitance

you will get best Q for shorter gate lengths, but narrower tuning range. refer to this paper. https://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1587923

 

[calculus_cuthbert]

how to reduce metal resistance in layout

While laying out MOS varactors and accumulation capacitor, I should do multi finger layout .. is that correct?? This would decrease the gate resistance right?? please correct me if I am wrong

 

[Pat_Mustard]

rf cmos layout

It is correct that this will reduce gate resistance. Split the gate into fingers and connect the fingers in metal, not polysilicon, as large areas of poly are more susceptible to failure during manufacture than smaller areas.

 

[sanredrose]

accumulation varactors

Multifingered device will reduce your gate resistance as well as the capacitance Cgs. So make sure you split it into the minimum number of fingers you need and nothing more. Adding more fingers will only reduce your Cgs more.