result from Cadence IC and hand calculation

[wesspower]

cadence model file gamma lambda

To all experts :

I have problem with id (drain current ) of nmos , I put the mos transistor in sat. mode , the connection is very simple , VDD connects to drain , Gnd connects to source, and apply 2 Volts into the gate. I use the equation Id = (Kp/2)(W/L)(Vgs-Vt)^2 *(1+lamba*Vds) , but the result of hand calculation is different with the result I got from Cadence Analog Artist.

Would some body please explain why and how to get the real id value by hand calculation . The spice model is model 1.

Thanks in advance

 

[mr_chip]

I did not understand from your post - are using SPICE Level 1 in Cadence?

 

[gunturikishore]

That may depend on your channel length. If your channel length is not too short ie say above 1u your model should work, beyond which I doubt the validity of the equations that Model 1 takes.

 

[Jayson]

Just make sure your value of kp, vt and lamda, is correct, these can be derived from the technology model file.

I've sucessfully done hand calculations using 0.18um TSMC technology, for my hand calculations I didn't even need to use the lambda term and the result was predictable in the simulator.

- Jayson

 

[BigBoss]

In the formulae, some technolgical parameters such as lambda, Vt etc. are really bias dependent. So hand calculations may differ so some iterative manipulations should be done.
In text books all parameters are assumed to be constant but ut's not really true...
To calculate by hand sometim becomes very tedious...

 

[wesspower]

Thanks for the repliers . Here is more information about my problem


I use specture of Cadence, the model is spice 1 , the value are vto = 1 , lamnba = 0.01, Kp = 16u, the W / L are 1.61u

5 volts directly apply to drain , the source is connected to gnd , and 2 volts apply to Gate. Body is connected with ground.

from the equation in the first post , I got Id = 8uA , but in specture of Cadence , I got more than 1mA for Id.


What was the problem ? Is my equation wrong ?

Thanks

 

[Vamsi Mocherla]

I really do not understand how can you get 8u current from your calculations. I am getting around 13.5u A from hand calculations using your equations. Is your W/L ratio 1.6 or is W=1.6u and L=1.6u. And finally in Cadence, is your transistor in saturation? One more small thing, try and put a Current source of about 8u on the drain and then try to get the transistor in saturation. What is the technology of your process? Please verify whether your transistors can operate at a 5 V at the drain......

 

[wesspower]

The width is 1.61u , and length is 1.61u. Vdd is 5 volts . , from the hand calculation , I got id is about 8u A

but in Cadence specture , I got id vaule is over 1mA.


the technology is 1.6u .

 

[Vamsi Mocherla]

Can you repeat the experiment with a bigger width device?I am not sure of the 1 mA result. It can only occur when the rds is about 5K ohm, which I think is not correct..

 

[wesspower]

I repeat the simulation with bigger than 1.61u , then the id is droping so quickly !!
when I set both Width and length are 2u , then id value is 80u .... I don't quite understand why this is happening like that . !! Please help me to understand.

 

[Jenifer_gao]

Hi:

You'd better check the technology option is correctly choosed in the cadence. That means the instance of the NMOS from this technology should allow 5V operation. You can use 0.35um, 0.5um or larger technology, but you can't use 0.25um, 0.18um or less.

J

 

[sutapanaki]

I haven't try to calculate the current, but 1ma is a bit high. Here is what you can do. Keep the same connections and Vgs=2v, but do a dc or transient sweep of the drain source voltage - instead of fixed Vdd, sweep this voltage. Then plot the current vs. Vds and you'll get the output characteristic of the transistor. See if it ever reaches 1ma and if it does where and why.

 

[wesspower]

I have done the dc analysis . I believe 1.6 is the technology I use . because I can not go lower than 1.61 in W and L , if I key in lower or equal to 1.6 , the simulator will show the error.

The model files I use for the simulation as below

simulator lang=spice
.model nmos nmos
+ level=1 vto=1 kp=16u gamma=1.3 lambda=0.01
+ phi=0.7 pb=0.80 mj=0.5 mjsw=0.3 cgbo=200p cgso=350p cgdo=350p
+ cj=300u cjsw=500p ld=0.8u tox=80n

.model pmos pmos
+ level=1 vto=-1 kp=8u gamma=0.6 lambda=0.02
+ phi=0.6 pb=0.50 mj=0.5 mjsw=0.25 cgbo=200p cgso=350p cgdo=350p
+ cj=150u cjsw=400p ld=0.8u tox=80n

 

[wesspower]

Sorry, guys , I finally understand the mos transistor now , because Leff = L - 2 * ld . , in my model the ld is too large .