[SOLVED] Resolving frequency mismatch problem

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rahdirs

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Hi,


I have a 10 bit dual ADC sampling at 1350 MHz.By using a 1:2 demux provided by the ADC supplier himself i can get 20 bits of data at 675 MHz(10 bits -> I & 10 bits -> Q).

I need to write this data into memory at 625 MHz.How can i get this to work.Yes,we can use zero padding.(extending a signal with zeroes).

Now that the problem has been explained,the fix here is 20 bits of ADC data can only be sent as 24 bits(12 bits -> I & 12 bits -> Q) or 32 bits(16 bits -> I & 16 bits -> Q).This is because we would generally like to use x8 or x16 data widths.
 

If I understand your problem, what you simply need to do is :

1) Sample your I data, store it in bits 0-9 of a 24-bit buffer
2) Sample your Q data, store it in bits 12-21 of the 24-bit buffer
3) Write your buffer to memory.
 

barry said:
Let's hope it's a typo, or FIFO here we come.
Click to expand...

No,it's not a typo.my i/p is at 675 MHz & o/p at 625 MHz.
The reason for this is,the memory i'm using,you could write it at a maximum of 667 MHz,so i'm trying to make it work at 625 MHz.

I was also thinking of FIFOs,but won't there be a overflow problem ?
 

I was also thinking of FIFOs,but won't there be a overflow problem ?
Click to expand...
Surely. It's a simple countable problem. The average input word rate must be less or equal than the output rate.

Is 625 MHz actually a maintained data rate or is it a dynamic RAM burst rate? And what's the total memory capacity?

Can accept some kind of data packing across word boundaries? Otherwise you need to switch to the next lower integer fraction, e.g. 30 bit at 450 MHz or 40 bit at 312.5 MHz.
 

Hi,
FvM said:
Is 625 MHz actually a maintained data rate or is it a dynamic RAM burst rate? And what's the total memory capacity?
Click to expand...

It will be by DDR3BurstRate.Memory size is not an issue(1 GB DDR3 SDRAM ).

FvM said:
Can accept some kind of data packing across word boundaries?
Click to expand...

I don't have much idea about data packing(will google it).But a quick search says it is space-time complexity,will there there be a delay of a large number of clock cycles ?
As long as there is no data-loss & i'm able to read it back,i have no problem.
 

Memory size is not an issue(1 GB DDR3 SDRAM ).
Click to expand...
Depends on the application. 1 GB gives you about 300 ms storage time with perfect data packing. I don't consider compression, just rearranging data bits. E.g. 16 x 20 bits packed into 5 x 64bit RAM words. 64-bit data rate would be 420 MHz if 20-bit input rate is 1350 MHz.
 

Hi,

Can i do something like this ? Store data in a fifo for 2-3 clk cycles(introducing delay),read from fifo at different clock frequency?
 

Hi,

Before finally marking this thread as solved,the solution to this problem was very easy.I used a FIFO(write depth = 2048) with independent rd & wr clocks.Write bus width = 128 bits & Read bus width = 256 bits.
So,even if i enable rd_en as high for a fraction of cycles for which wr_en was high, i will not have problem of overflow.

P.S: Data i/p is in burst form.
 

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