ErenYeager97
Newbie level 5
Hi I am making an on-chip analog circuit of which one-part is as shown below:
M1 is a big PMOS transistor charging C1 in one phase of clock and in the other phase C1 is discharged by an NMOS connected to it.
The idea is to develop a negative voltage at the bottom of C1 in such a way so it is only shown to be grounded in the picture
but not in the actual circuit.
The problem is that resistive level shifter signal at the gate of PMOS shows glitches which happen some time later at both turn ON and OFF of the PMOS. It looks like the following:
I think this is due to the big gate capacitance of the PMOS but I don't know how to fix this
M1 is a big PMOS transistor charging C1 in one phase of clock and in the other phase C1 is discharged by an NMOS connected to it.
The idea is to develop a negative voltage at the bottom of C1 in such a way so it is only shown to be grounded in the picture
but not in the actual circuit.
The problem is that resistive level shifter signal at the gate of PMOS shows glitches which happen some time later at both turn ON and OFF of the PMOS. It looks like the following:
I think this is due to the big gate capacitance of the PMOS but I don't know how to fix this