Resistive Level Shifter for Power PMOS

[ErenYeager97]

Hi I am making an on-chip analog circuit of which one-part is as shown below:

M1 is a big PMOS transistor charging C1 in one phase of clock and in the other phase C1 is discharged by an NMOS connected to it.
The idea is to develop a negative voltage at the bottom of C1 in such a way so it is only shown to be grounded in the picture
but not in the actual circuit.

The problem is that resistive level shifter signal at the gate of PMOS shows glitches which happen some time later at both turn ON and OFF of the PMOS. It looks like the following:

I think this is due to the big gate capacitance of the PMOS but I don't know how to fix this

 

[KlausST]

Hi,

From your description the schematic is not complete.
Also the waveform makes no sense .. with the given circuit.

And the timing of the waveform? Are we talking about picoseconds, microseconds, seconds?
Is it a simulation (with ideal power supplies) .. or a real circuit? then how did you measure it (testing conditions)?

To be able to give good feedback we need to have full informations first.

**
Talking about absolute gate voltage of M1 is not very useful when discussing circuit functionality. A MOSFET works on V_GS (the voltage between gate and source).
Thus if you provide a graph for "absolute" V_Gate, then you also need to provide a graph with "absolute" voltage of V_Source .. to find out what´s happening.

Klaus