Reset of syncronizing flip flops

Status
Not open for further replies.
S

sun_ray

Advanced Member level 3
Joined
Oct 3, 2011
Messages
772
Helped
5
Reputation
10
Reaction score
5
Trophy points
1,298
Visit site
Activity points
6,828
Hi the attached picture shows a reset where the reset is removed syncronously. What about the rest of this two flip fllops that works as a synchronizer.
 

Attachments

  • res.JPG
    15.6 KB · Views: 233
Last edited:

For active low reset, the data pin will be tied to Vcc(high), the reset pin of the two FF will be connected to reset only. This will provide helps to avoid removal violation. when reset is applied, all the Flops will be put into reset state.
 
The above circuit if for a active high rest and not for an active low rest. Do you want to mean the reset that comes from outside will be connected to the flipflops? Do you mean otherwise that these tow flip flops will have reset from the output of the OR gate?
 

if it is active high then, then provide data as zero.
Do you want to mean the reset that comes from outside will be connected to the flipflops?
yes
 

I have modified the figure with pin names changed. Which pin do you refer to by saying data input? This circuit cannot be a active high circuit with R input as zero. This circuit is for a active low rest and not for a active high reset.
 

this article may be useful :

**broken link removed**

"The reset signal is usually as loaded as your clock net. If you don't take care on your clock net, it will soon bite you as this net is clocking your design every cycle, when clock is enabled...."
 

process(clk,reset)
begin
if (resest = '1') then
d <= '1';
d_dly <= '1';
end if
else
d <= '0';
d_dly <= d;
end if
end

d_dly is the R_Q as in figure
Syntax may be wrong. Please check it
 

shanmugaveld

I do not understand the purpose of this code. What is 'd' in your code? I still do not get the answer about the reset signal of the syncronizing double flipflops in my figure. Can you or anyoone answer?
 

Reactions: FvM

    FvM

    Points: 2
    Helpful Answer Positive Rating
That paper and these are known to me. You are not answering the question.
 

sun_ray said:
Hi the attached picture shows a reset where the reset is removed syncronously. What about the rest of this two flip fllops that works as a synchronizer.
Click to expand...

To avoid the metastability of flip-flops in your design because of rest, reset should be asynchronously activated and synchronously deactivated.
For detail of this explaination you can refer my replies in below tread.
https://www.edaboard.com/threads/224800/#post959860

Now (assuming active high reset) in your code reset is getting activated asynchronously, and desertion of reset is synchronously, so according to me your circuit will work.
 

My Understanding about your query is
"reason for synchronizing the reset", in 2,9,11 replies reasons are explained.
 

THAT WAS NOT THE QUESTION.

The question is: The R_Q of the figure will go to rest pins of all the flip flops in the design and rest them accordingly when reset comes. But, where are the reset pins of the two syncronizing flipflops that are shown in the above figure connected to? Are they connected to R_Q pin of the figure? Or, are they connected to R pin of the figure? If not, where are these two reset pins of these two synchornizing flipflops connected to?

Regards
 

I would suggest to think your self and write your opinion here, that is best way of learning if you are wrong then you will be corrected....

This is very simple think over it..
 
Reactions: FvM

    FvM

    Points: 2
    Helpful Answer Positive Rating
That paper and these are known to me. You are not answering the question.
Click to expand...
You either didn't read or not understand it.

The usual reset synchronizer known from literature, which is also shown in the sunburst paper is different from your scheme. It connects the asynchronous reset (or preset, depending on the reset polarity) of the synchronizer FFs to the reset input.

In your scheme, if you prefer it for some reason, you can simply leave the reset unconnected. But you should connect the clock, by the way.
 

In the Figure both FF's are FF with synchronous resets.
Data will be driven with mux with reset as select line or with NAND or AND gates
Check below links to know how data are driven in FF with sync.resets
All About Reset
**broken link removed**
 


Yes, very true.
 

shitansh, fvm

I read the paper. The paper does not mention about reset in flip flops of my circuit whose figure was shown at the beginning of the thread. Can you please mention the page and paragraph number where the paper mentions about reset in flip flops of my circuit whose figure was shown at the beginning of the thread, if the paper write about that. The paper writes about a reset circuit different that mine but I do not find where the paper answers my question in this thread.

FVM

In your scheme, if you prefer it for some reason, you can simply leave the reset unconnected. But you should connect the clock, by the way.
Click to expand...

Will it be sufficient if the reset are unconnected in my diagram because then the flipflops cannot be reset when wanted?
shanmugaveld


Will it be sufficient if we drive the reset of these flipflops by sync reset as mentioned by you. In that case here there is no data and so how the data input of the Mux or the AND gate will be connected here?
 

Viewing the thread with one year distance, I think the main problem is that besides an incomplete schematic, no specific purpose of the circuit (e.g. related to standard reset synchronizers from literature) has been mentioned. Thus we can only guess about expectable clock and reset input waveforms. The question "should the FF resets be connected" (to the same reset driving the D input?) brings up the counter question: What's the reason not to use a standard reset synchronizer?
 


So let me clarify the ambiguities you have one after another.

Firstly the shematic is complete and I only want to know about the reset of the two flipflops. The reset of the two flipflops is the only incompleteness in the schematic and that is one of the main reasons I started this thread.

Secondly, the only purpose of the schematic is to send a reset to a digital system where reset should be asynchronously asserted and synchronously deasserted. The attached diagram or schematic serves that purpose.

Thirdly, a standard reset synchronizer as shown in the attached paper can also be used but this schematic also serves the same purpose as the standard reset synchronizer does in the paper.

Fourthly, this schematic is also a schematic that can serve the purpose of a standard reset synchronizer as described in the attached paper. So why not to use it?

Please let me know if you have more ambiguities or queries.

But my question is about the reset mechanism of the two flipflops in my attached diagram. Is it sufficient if resets are not connected for the flipflops in my diagram as stated by you?

Regards
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…