Research on challenges in Analog Layout design

[pmotakef]

Hi All,

We are a technology development team funded by the U.S. National Science Foundation (NSF). We are trying to learn about the challenges in Analog IC layout design process, especially experiences with the available EDA tools, and the good, the bad, and the ugly of the design process. This is purely educational for us and we are trying to learn from layout designer experts. We appreciate the opportunity for a quick chat.

If you are willing to share your insights, please let me know.

[Direct contact info deleted according to forum rules]

Thanks a lot.
Pouya

 

[dick_freebird]

The challenges are that

(1) lots of things matter (more than just max clock,
max gate count and power) and you have no idea
which until you're in it

(2) everything but frequency gets crappier the
lower in device-size you go, and "automation"
that just turns the crank on device properties
until conditions are met may optimize you to
the criteria you knew to assert, and a blind eye
to anything you didn't. I've seen outfits who
claim big analog process-retargeting ability but
the op amps they produce by that way of working,
were really really bad. Like AVOL=40dB and
input common mode range almost nil (because
supply headroom has contracted faster than
FET VT for no-leak), and by 0.9V core there's
nothing left for a non-R2R front and back end.

(3) There's no real problem with layout tools.
There's a problem with management and CAD
sales douches banging the throughput drum
and believing you can replace hard-won talent
with cheap H-1B / fresher slave labor and the
"right" tools. The effort of delivering all the data
and rules for any tool to act at all "right", of
course, is not discussed because it would be
a real short meeting.

If you want to suggest an avenue, maybe think
about that last bit. Assistive layer above the
"enter the upper and lower limit" panel for
optimizers, that would let the low-info user
"just pick" from canonical care-abouts lists
for various analog functions? Assistive layer
below, which might start substituting classic
(or new, if you've got) topologies (for the case
that the technology you "shall" use, has left
the transistor qualities you need for the outcome
you want, in the ditch in your rear view mirror -
leaving you to find the path, not just tweak
around the edges of "what worked last time".