library(myWLM) {
/* zero wire-load */
wire_load("zero") {
resistance : 0;
capacitance : 0;
area : 1;
slope : 1;
fanout_length(1,2000);
}
}
library(2K_6LM) {
wire_load("2K_6LM") {
resistance : 1.2;
capacitance : 0.2;
area : 1;
slope : 1;
fanout_length(1,2000);
fanout_length(2,2500);
fanout_length(3,3000);
fanout_length(4,4000);
fanout_length(5,5000);
fanout_length(6,6000);
fanout_length(7,7000);
fanout_length(6,8000);
}
}
How the tool knows which RC pair to take just from the cells placement? Does it calculate the wire length?Cap-table just keeps RC data for each metal layers - no any relations to fanout or (just RC per wire width, wire spacing, metal layer number ...)
So, what usually does happen? How many WLM models are usually supplied with STD Cell libraries? Are there WLM, which depend on geometry of the design? on gates-count?WLM has different tables per gate count (or just one table for any design).
So, what usually does happen? How many WLM models are usually supplied with STD Cell libraries? Are there WLM, which depend on geometry of the design? on gates-count?WLM has different tables per gate count (or just one table for any design).
And what about the placement-not-aware tools like a regular Design Compiler from Synopsys? How do these tools know how to take the right values from the WLM? They are not aware of the wires length, are not them?tool that does placement (for example Synopsys DC-topographical or IC Compiler) is able to esimate each wire length after placement
Could you give me some number (in %) how much space do you reserve for these purposes?we reserve some free space for new cells (clock cells, additional buffers for hold fixing ...)
From taking a look on the WLM, which I have, I don't see ever a clue about the gates count - there are only relations between a fanout and wire length. So, it's still not understood for me how WLM depends on gate-count... In the theory it's clear, but in the practice... Where is gate-count information stored in the WLM? Could you please provide an example or lines from your WLMs?Yes, gates-count per say area for that specific module and not geometry of the design.
What's the LEF files? What info do they store?it uses LEF and Cap-table files
wire_load_selection(WireArea){
wire_load_from_area(0, 17134, "WLM8K");
wire_load_from_area(17134, 38552, "WLM16K");
}
wire_load("WLM8K") {
resistance : 0.00001 ;
capacitance : 1 ;
area : 0
slope : 0.0010
fanout_length(1,0.0011)
fanout_length(2,0.0019)
fanout_length(3,0.0029)
fanout_length(4,0.0040)
fanout_length(5,0.0053)
}
wire_load("WLM16K") {
resistance : 0.00001 ;
capacitance : 1 ;
area : 0
slope : 0.0011
fanout_length(1,0.0011)
fanout_length(2,0.0020)
fanout_length(3,0.0031)
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