Requesting help for reading from file assignment

Status
Not open for further replies.
S

Slayer1234

Newbie level 3
Joined
Feb 5, 2014
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Visit site
Activity points
73
Hi guys,its my first time here in this forum.Firstly,nice to meet you all.I would like to request help for my assignment as I am having difficulties at one part of my assignment.

I am trying to read from a file that has 3 columns,and I only need the middle column,So I declared 2 extra variables to store the left and right column while another variable(for my input)is used for the middle column.Attached is my input file and below is my code(reading part).Any help is greatly appreciated and thanks for taking your time to read my post.

Input File
____________________
View attachment input8.txt


Code
__________________
Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

process 
use std.textio.all;
use ieee.numeric_std.all;
file inputfile:text open read_mode is "input8.txt";
 
variable ipa:std_logic_vector(63 downto 0);
variable ipb:std_logic_vector(63 downto 0);
variable inline:line;  
variable ipc:character;    
    
        begin
            while not(endfile(inputfile))loop
                readline(inputfile,inline);
                hread(inline,ipa);
               --data_in<=ipa;
                hread(inline,ipb);
                data_in<=ipb;               
                read(inline,ipc);
               --data_out2<= std_logic_vector(to_unsigned(character'pos(ipc),data_out2'length));
                wait for 800 ns;
              
          end loop;
          wait;
          end process;
 
Last edited by a moderator:

The code you have posted is not complete:

There is no entity declaration.
There is no architecture.
There is no start to the process.

So please post the full code and state what the problems are.

- - - Updated - - -

You also have not included the correct libraries for the functions and types you are using
 

Hi Tricky,Below is my full code,I am doing a Encryption project using VHDL,The full code is fine except the reading part.My guess is because halfway through the input file,The left and right column is empty while the middle column is still continuing.I have actually completed the project but my Instructor told me to add reading from file feature to get more bonus points.Please view the input file attachment as I am unable to show it here.
Thanks for your reply!


Code
_________
Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191

library IEEE;
    Use IEEE.std_logic_1164.all;
    use IEEE.std_logic_unsigned.all;
    use IEEE.std_logic_textio.all;
    use IEEE.numeric_std.all;
    entity des_cipher_top_tb is end;
    architecture key of des_cipher_top_tb is 
    
    component des_cipher_top port(
        
        key:        in std_logic_vector(0 to 63);
 
        -- 
        -- function select
        --
        function_select:    in  std_logic; -- active when encryption, inactive when decryption
 
        --
        -- input into des_cipher_top 
        --      
        data_in:        in std_logic_vector(0 to 63);
 
        --
        -- input into des_cipher_top 
        --      
        data_out:   out std_logic_vector(0 to 63);
 
        --
        -- data interface to MCU
        --  
 
        --
        -- General clock and reset
        --
        start_keyschedule: in std_logic;
        start: in std_logic;
        reset: in std_logic;
        clock: in std_logic
    );
end component;
 
 
 
 
    signal reset, start,start_keyschedule: std_logic;
    signal clock: std_logic := '0'; 
    
    signal key:std_logic_vector(0 to 63);
    signal function_select:     std_logic; 
    signal data_in:      std_logic_vector(0 to 63);
    signal data_out:     std_logic_vector(0 to 63);
    
        signal key_in_internal: std_logic_vector(0 to 63);
    signal memkey: std_logic_vector(0 to 63);
    
    signal data_in_internal: std_logic_vector(0 to 63);
    signal data_out_internal: std_logic_vector(0 to 63);
    
 
  begin
 
 
    
    
       u1:des_cipher_top port map(reset=>reset, clock=>clock, function_select=>function_select,
                        key=>key,data_in=>data_in,data_out=>data_out,
                        start=>start,start_keyschedule =>start_keyschedule); 
           start<=  '0' , 
               '1' after 600 ns,
               '0' after 610 ns,
               '1' after 1400 ns,
               '0' after 1410 ns,
               '1' after 2200 ns,
               '0' after 2210 ns,
               '1' after 3000 ns,
               '0' after 3010 ns,
               '1' after 3800 ns,
               '0' after 3810 ns,
               '1' after 4600 ns,
               '0' after 4610 ns,
               '1' after 5400 ns,
               '0' after 5410 ns,
               '1' after 6200 ns,
               '0' after 6210 ns,
               '1' after 7000 ns,
               '0' after 7010 ns,
               '1' after 7800 ns,
               '0' after 7810 ns,
               '1' after 8600 ns,
               '0' after 8610 ns,
               '1' after 9400 ns,
               '0' after 9410 ns,
               '1' after 10200 ns,
               '0' after 10210 ns,
               '1' after 11000 ns,
               '0' after 11010 ns,
               '1' after 11800 ns,
               '0' after 11810 ns,
               '1' after 12600 ns,
               '0' after 13400 ns,
               '1' after 13410 ns,
               '0' after 14200 ns,
               '1' after 14210 ns,
               '0' after 15000 ns,
               '1' after 15010 ns,
               '0' after 15800 ns,
               '1' after 15810 ns,
               '0' after 16600 ns,
               '1' after 16610 ns,
               '0' after 17400 ns,
               '1' after 17410 ns,
               '0' after 18200 ns,
               '1' after 18210 ns,
               '0' after 19000 ns,
               '1' after 19010 ns,
               '0' after 19800 ns,
               '1' after 19810 ns;
            
            start_keyschedule <=  '0',
                     '1' after 75 ns,
                     '0' after 85 ns;  
               
               
          reset<= '1', '0' after 50 ns;
                   --'1' after 4500 ns,
                  -- '0' after 4550 ns;
          clock<= not clock after 5 ns;
    
          
          --data_in <= x"785AC3A4BD0FE12D",
                    -- x"123456789ABCDEF0" after 1400 ns,
                     --x"785AC3A4BD0FE12D" after 2200 ns;
           --data_in <= x"FD9CBA5D26331F38",
                    --x"17EA4A8B48C14DA0" after 1400 ns,
                    --x"FD9CBA5D26331F38" after 2200 ns;
                    
process 
use std.textio.all;
use ieee.numeric_std.all;
file inputfile:text open read_mode is "input8.txt";
 
variable ipa:std_logic_vector(63 downto 0);
variable ipb:std_logic_vector(63 downto 0);
variable inline:line;  
variable ipc:character;    
    
        begin
            while not(endfile(inputfile))loop
                readline(inputfile,inline);
                hread(inline,ipa);
                --data_in<=ipa;
                hread(inline,ipb);
                data_in<=ipb;               
                read(inline,ipc);
                --data_in<= std_logic_vector(to_unsigned(character'pos(ipc),data_in'length));
                wait for 800 ns;
              
          end loop;
          wait;
          end process;
                  
          
                         function_select <= '0';
                            --'0' after 2100 ns,
                            --'1' after 4550 ns;
                            --'0' after 5800 ns;
 
                  
           tb: PROCESS
       BEGIN
         key <= x"38A84FF898B90B8F";
         wait for 1400 ns;
      
          
        end process;
        
process
use std.textio.all;
use ieee.numeric_std.all;
file resultfile:text open write_mode is "result.txt";
variable outline:line;
variable outline1:line;
 
begin
                wait on data_out;
                wait for 50 ns;
                write(outline,now,right, 2);
                hwrite(outline,data_out,right,40);
                writeline(resultfile,outline);
                end process;
         end key;
 
Last edited by a moderator:

I am using modelsim,and when I stimulate the code,It shows the input as 000000(all zeros)....I tested by using the left Column as my input and just store the other 2 columns(middle,right)into variables and it works.

So was wondering if it is possible to read the middle column although the other two columns are empty halfway through the input file?Thanks for reading and looking forward to your reply.
 

The input file needs to have 3 columns all the way down the file for it to work, otherwise it will fail a read, and as you havent set it up to detect read failures, I think it will return 0 (maybe even all 'U') as you have seen.

The read/hread functions work by reading the line up to the next whitespace. So if there is only 1 value on the line, the value will be read into the first variable.
 

Yes I found that out too,My instructor then changed a different input file for me,But now I am still unable to read the file.I tried reading the middle/right column seperately and it works.The problem lies with the left column,I think it is because my encryption project can only do 64-bit inputs,while the left column is 32 bit,Is there anyway I can solve this issue?

Input file
______________
00000000 FFD8FFE000104A464946000101000001 ÿØÿà.JFIF...
00000010 00010000FFDB00840009060714131214 ...ÿÛ.„..
00000020 14121416151515151816171717171817 
00000030 1718181418181717181817181E282019 ( 
00000040 1A251F181721312226292B2E2E2E171F %!1"&)+...
00000050 3338332C37282D2E2B010A0A0A0E0D0E 383,7(-.+
00000060 1B10101B342420242C352C322F302C2C 4$ $,5,2/0,,
 

THis looks like a hex representation of the file. Is it a text file or binary file? textio can only read text files.
 



you need to tell the file that is it a hexadecimal value. use x"00000000" which shows that the data is a hexadecimal value. why do you have symbols and other foreign characters in your text file?
 

You dont tell the file anything. You also dont tell the VHDL what the format is. You use different functions/procedures to read in hex or binary or octal.
The file posted by the OP looks like what a decent text editor shows when it opens a non-text file. The left column is the file address, the middle column is the raw binary data and the right column is the data represented as ascii characters.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…