[SOLVED] Request for clarification: multiplication and hardware multipliers blocks

[FlyingDutch]

Hello everybody,

there is one question not clear for me related to multiplication in HDL code (VHDL or Verilog) and further synthesis. Let assume that we have two integers (for example 16 bit unsigned) a and b. Then we use VHDL code with multiplying operator * :

x:= a*b;

Would the result be calculated with using hardware multiplier block from FPGA fabrick or not? And what if the number of multiplication operation we have to calculate is bigger than the number of hardware multiplication blocks in FPGA (for example Spartan3A - XC3S50 has only four such blocks)?

I am asking in context of matrix multiplification on FPGA. I need matrix multiplification for amateur robotic arm - for calculating position in 3D using quadrature encoders mounted on arm joints.

I would also ask if this implementation of "matrix multiplication" is implemented efficient (or are better implementations or methods):

https://www.fpga4student.com/2016/11/matrix-multiplier-core-design.html

Thanks in advance and regards.

 

[dpaul]

Would the result be calculated with using hardware multiplier block from FPGA fabrick or not?

Yes the internal MUL block of the FPGA will be inferred.

 

[TrickyDicky]

Usually, it will infer a DSP block, with surrounding pipeline registers also sucked into the DSP block (or at least it should). It should also be able to infer the carry chain as needed.
If DSP run out, it should also be able to infer logic multipliers.

The user can usually direct synthesis to either by using attributes.

So features of a DSP block may not be inferable - you will need to read your chip documentation.

 

[FlyingDutch]

The user can usually direct synthesis to either by using attributes.

Hello,

what atribute I should use to literally inform synthesis software that multiplication have to be run on DSP block?

Regards

 

[filip.amator]

Hello,

what atribute I should use to literally inform synthesis software that multiplication have to be run on DSP block?

Regards

It depends on your tool -- read the manual.

 

[dpaul]

Read the UG901 first.

Using the operator * will infer the DSP48 block (not sure if it is also DSP48 for Spartan3, but will be a similar block). However if you still want to be sure, use the attribute USE_DSP48 or just USE_DSP(recommended).
The Xilinx synth tool should be smart enough to build a pipelined multiplier from the fabric given some number of pipe stages on the output. Again the pipe stage placement is up to the synthesis tool as long as you don't specifically use intermediate results.