Representation in big endian form using vhdl

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The probable solution:
1. 1023 downto 0 instead of 0 to 1023
 

man it is conventional if i write message2(511 downto 0 ) or messega2(0 to 511)...
Anyhow i write it i am gonna change the code so that in the simulation i see that message2 is "message1&1&0...0&128-bit binary representation of the length of the message1 in big endian form".
 

ok guys ! i solved my problem! Thanks again for your help! Finally the solution to my problem had to do with something else and not with the padding of the message! Anyway thanks for your help! Now my problem is how to give during the simulation as an input a variable length message! I am going to open a new thread for this different problem.
 

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